MSP430F6638 Datasheet, PDF (48/126 Pages) Texas Instruments – Mixed-Signal Microcontrollers

MSP430F6638, MSP430F6637, MSP430F6636, MSP430F6635
MSP430F6634, MSP430F6633, MSP430F6632, MSP430F6631, MSP430F6630
SLAS566E – JUNE 2010 – REVISED DECEMBER 2015
www.ti.com
5.45 12-Bit DAC, Supply Specifications
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
AV_CC Analog supply voltage
TEST CONDITIONS
AV_CC = DV_CC, AV_SS = DV_SS = 0 V
DAC12AMPx = 2, DAC12IR = 0,
DAC12OG = 1,
DAC12_xDAT = 0800h,
VeREF+ = VREF+ = 1.5 V
V_CC
MIN TYP MAX UNIT
2.20
3.60 V
3V
65 110
I_DD
Supply current, single DAC channel^{(1) (2)}
PSRR Power supply rejection ratio^{(3) (4)}
DAC12AMPx = 2, DAC12IR = 1,
DAC12_xDAT = 0800h,
VeREF+ = VREF+ = AV_CC
DAC12AMPx = 5, DAC12IR = 1,
DAC12_xDAT = 0800h,
VeREF+ = VREF+ = AV_CC
DAC12AMPx = 7, DAC12IR = 1,
DAC12_xDAT = 0800h,
VeREF+ = VREF+ = AV_CC
DAC12_xDAT = 800h,
VeREF+ = 1.5 V, ΔAV_CC = 100 mV
DAC12_xDAT = 800h,
VeREF+ = 1.5 V or 2.5 V,
ΔAV_CC = 100 mV
2.2 V, 3 V
2.2 V
3V
125 165
µA
250 350
750 1100
70
dB
70
(1) No load at the output pin, DAC12_0 or DAC12_1, assuming that the control bits for the shared pins are set properly.
(2) Current into reference terminals not included. If DAC12IR = 1 current flows through the input divider; see Reference Input specifications.
(3) PSRR = 20 log (ΔAV_CC / ΔV_{DAC12_xOUT})
(4) The internal reference is not used.
5.46 12-Bit DAC, Linearity Specifications
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-17)
INL
DNL
PARAMETER
Resolution
Integral
nonlinearity ⁽¹⁾
Differential
nonlinearity ⁽¹⁾
TEST CONDITIONS
12-bit monotonic
VeREF+ = 1.5 V, DAC12AMPx = 7, DAC12IR = 1
VeREF+ = 2.5 V, DAC12AMPx = 7, DAC12IR = 1
VeREF+ = 1.5 V, DAC12AMPx = 7, DAC12IR = 1
VeREF+ = 2.5 V, DAC12AMPx = 7, DAC12IR = 1
V_CC
2.2 V
3V
2.2 V
3V
MIN TYP MAX UNIT
12
bits
±2 ±4⁽²⁾
LSB
±2
±4
±0.4
±0.4
±1 ⁽²⁾
LSB
±1
Without calibration^{(1) (3)}
E_O
Offset voltage
With calibration^{(1) (3)}
VeREF+ = 1.5 V,
DAC12AMPx = 7,
DAC12IR = 1
VeREF+ = 2.5 V,
DAC12AMPx = 7,
DAC12IR = 1
VeREF+ = 1.5 V,
DAC12AMPx = 7,
DAC12IR = 1
VeREF+ = 2.5 V,
DAC12AMPx = 7,
DAC12IR = 1
2.2 V
3V
2.2 V
3V
±21 ⁽²⁾
±21
mV
±1.5 ⁽²⁾
±1.5
d_E(O)/d_T
Offset error
temperature
coefficient ⁽¹⁾
With calibration
2.2 V, 3 V
±10
µV/°C
E_G
Gain error
VeREF+ = 1.5 V
VeREF+ = 2.5 V
2.2 V
3V
±2.5
%FSR
±2.5
(1) Parameters calculated from the best-fit curve from 0x0F to 0xFFF. The best-fit curve method is used to deliver coefficients "a" and "b" of
the first-order equation: y = a + bx. V_{DAC12_xOUT} = E_O + (1 + E_G) × (VeREF+ / 4095) × DAC12_xDAT, DAC12IR = 1.
(2) This parameter is not production tested.
(3) The offset calibration works on the output operational amplifier. Offset calibration is triggered by setting the DAC12CALON bit.
48
Specifications
Copyright © 2010–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F6638 MSP430F6637 MSP430F6636 MSP430F6635 MSP430F6634 MSP430F6633
MSP430F6632 MSP430F6631 MSP430F6630