MSP430F6638 Datasheet, PDF (38/126 Pages) Texas Instruments – Mixed-Signal Microcontrollers

MSP430F6638, MSP430F6637, MSP430F6636, MSP430F6635
MSP430F6634, MSP430F6633, MSP430F6632, MSP430F6631, MSP430F6630
SLAS566E – JUNE 2010 – REVISED DECEMBER 2015
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5.33 USCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾
(see Figure 5-13 and Figure 5-14)
PARAMETER
t_STE,LEAD
STE lead time, STE low to clock
TEST CONDITIONS
PMMCOREV = 0
PMMCOREV = 3
V_CC
1.8 V
3V
2.4 V
3V
MIN MAX UNIT
11
8
ns
7
6
t_STE,LAG
STE lag time, Last clock to STE high
PMMCOREV = 0
PMMCOREV = 3
1.8 V
3
3V
3
ns
2.4 V
3
3V
3
t_STE,ACC
STE access time, STE low to SOMI data out
PMMCOREV = 0
PMMCOREV = 3
1.8 V
3V
2.4 V
3V
66
50
ns
36
30
t_STE,DIS
STE disable time, STE high to SOMI high
impedance
PMMCOREV = 0
PMMCOREV = 3
1.8 V
3V
2.4 V
3V
30
23
ns
16
13
t_SU,SI
SIMO input data setup time
PMMCOREV = 0
PMMCOREV = 3
1.8 V
5
3V
5
ns
2.4 V
2
3V
2
t_HD,SI
SIMO input data hold time
PMMCOREV = 0
PMMCOREV = 3
1.8 V
5
3V
5
ns
2.4 V
5
3V
5
t_VALID,SO
SOMI output data valid time⁽²⁾
UCLK edge to SOMI valid,
C_L = 20 pF,
PMMCOREV = 0
UCLK edge to SOMI valid,
C_L = 20 pF,
PMMCOREV = 3
1.8 V
3V
2.4 V
3V
76
60
ns
44
40
t_HD,SO
SOMI output data hold time⁽³⁾
C_L = 20 pF,
PMMCOREV = 0
C_L = 20 pF,
PMMCOREV = 3
1.8 V
18
3V
12
ns
2.4 V
10
3V
8
(1) f_UCxCLK = 1/2t_LO/HI with t_LO/HI ≥ max(t_{VALID,MO(Master)} + t_SU,SI(USCI), t_{SU,MI(Master)} + t_{VALID,SO(USCI)}).
For the master parameters t_{SU,MI(Master)} and t_{VALID,MO(Master)}, see the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in Figure 5-13 and Figure 5-14.
(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 5-13
and Figure 5-14.
38
Specifications
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