MSP430F5310 Datasheet, PDF (6/106 Pages) Texas Instruments – MSP430F5310 and MSP430F530x Mixed-Signal Microcontrollers

MSP430F5310, MSP430F5309
MSP430F5308, MSP430F5304
SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013
www.ti.com
Functional Block Diagram – MSP430F5310IRGZ, MSP430F5309IRGZ, MSP430F5308IRGZ,
MSP430F5310IPT, MSP430F5309IPT, MSP430F5308IPT
XIN XOUT RST/NMI DVCC DVSS VCORE AVCC AVSS
PA
PB
PC
P1.x P2.x P3.x P4.x P5.x P6.x
XT2IN
XT2OUT
Unified
Clock
System
ACLK
SMCLK
MCLK
32KB
24KB
16KB
Flash
CPUXV2
and
Working
Registers
MAB
MDB
6KB
RAM
Power
SYS
Management _Watchdog
LDO
SVM/SVS
Brownout
Port Map
Control
(P4)
I/O Ports
P1, P2
1×8 I/Os
1×1 I/Os
Interrupt,
Wakeup
PA
1×9 I/Os
I/O Ports
P4
1×8 I/Os
PB
1×8 I/Os
I/O Ports
P5, P6
1×6 I/Os
1×4 I/Os
PC
1×10 I/Os
REF
COMP_B
ADC10_A
10 Bit
200 KSPS
8 Channels
(6 ext, 2 int)
Window
Comparator
DMA
3 Channel
EEM
(S:3+1)
JTAG,
SBW
Interface
MPY32
TA0
Timer_A
5 CC
Registers
TA1
Timer_A
3 CC
Registers
TA2
Timer_A
3 CC
Registers
TB0
Timer_B
7 CC
Registers
RTC_A
CRC16
USCI
A1: UART,
IrDA, SPI
B1: SPI, I2C
PU Port
LDO
PU.0, PU.1
6
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