MSP430F5310 Datasheet, PDF (12/106 Pages) Texas Instruments – MSP430F5310 and MSP430F530x Mixed-Signal Microcontrollers

MSP430F5310, MSP430F5309
MSP430F5308, MSP430F5304
SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013
www.ti.com
Table 2. Terminal Functions (continued)
TERMINAL
NAME
NO.
I/O ⁽¹⁾
RGC
RGZ,
PT
ZQE
DESCRIPTION
P4.5/PM_UCA1RXD/
PM_UCA1SOMI
General-purpose digital I/O with reconfigurable port mapping secondary
46
34
C9
I/O
function
Default mapping: Receive data – USCI_A1 UART mode
Default mapping: Slave out, master in – USCI_A1 SPI mode
P4.6/PM_NONE
General-purpose digital I/O with reconfigurable port mapping secondary
47 35 C8 I/O function
Default mapping: no secondary function.
P4.7/PM_NONE
General-purpose digital I/O with reconfigurable port mapping secondary
48 36 C7 I/O function
Default mapping: no secondary function.
VSSU
49
37
B8,
B9
PU ground supply
PU.0
50 38 A9 I/O General-purpose digital I/O - controlled by PU control register
NC
51 39 B7 I/O No connect.
PU.1
52 40 A8 I/O General-purpose digital I/O - controlled by PU control register
LDOI
53 41 A7
LDO input
LDOO
54 42 A6
LDO output
NC
55 43 B6
No connect.
AVSS2
56 44 A5
Analog ground supply
P5.2/XT2IN
57
45
B5
I/O
General-purpose digital I/O
Input terminal for crystal oscillator XT2
P5.3/XT2OUT
58
46
B4
I/O
General-purpose digital I/O
Output terminal of crystal oscillator XT2
TEST/SBWTCK
59 47 A4
I
Test mode pin – select digital I/O on JTAG pins
Spy-bi-wire input clock
PJ.0/TDO
60
23
C5
I/O
General-purpose digital I/O
Test data output port
PJ.1/TDI/TCLK
61
24
C4
I/O
General-purpose digital I/O
Test data input or test clock input
PJ.2/TMS
62
25
A3
I/O
General-purpose digital I/O
Test mode select
PJ.3/TCK
RST/NMI/SBWTDIO
63
26
B3
I/O
General-purpose digital I/O
Test clock
Reset input active low⁽³⁾
64 48 A2 I/O Non-maskable interrupt input
Spy-bi-wire data input/output
P6.0/CB0/A0
General-purpose digital I/O
1
1 A1 I/O Comparator_B input CB0 (not available on F5304 device)
Analog input A0 – ADC
P6.1/CB1/A1
General-purpose digital I/O
2
2 B2 I/O Comparator_B input CB1 (not available on F5304 device)
Analog input A1 – ADC
P6.2/CB2/A2
General-purpose digital I/O
3
3 B1 I/O Comparator_B input CB2 (not available on F5304 device)
Analog input A2 – ADC
P6.3/CB3/A3
Reserved
General-purpose digital I/O
4
4 C2 I/O Comparator_B input CB3 (not available on F5304 device)
Analog input A3 – ADC
N/A N/A
(4)
Thermal Pad
Pad Pad N/A
Exposed thermal pad on QFN packages. Connection to V_SS is recommended
(not available on PT package devices).
(3) When this pin is configured as reset, the internal pullup resistor is enabled by default.
(4) C6, D4, D5, D6, E3, E4, E5, E6, F3, F4, F5, F6, F7, F8, G3 are reserved and should be connected to ground.
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