MSP430F5310 Datasheet, PDF (58/106 Pages) Texas Instruments – MSP430F5310 and MSP430F530x Mixed-Signal Microcontrollers

MSP430F5310, MSP430F5309
MSP430F5308, MSP430F5304
SLAS677E – SEPTEMBER 2010 – REVISED NOVEMBER 2013
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USCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
t_τ
UART receive deglitch time ⁽¹⁾
TEST CONDITIONS
V_CC
2.2 V
3V
MIN TYP
50
50
MAX
600
600
UNIT
ns
(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized, their duration should exceed the maximum specification of the deglitch time.
USCI (SPI Master Mode) Recommended Operating Conditions
PARAMETER
CONDITIONS
V_CC
f_USCI
USCI input clock frequency
Internal: SMCLK, ACLK
Duty cycle = 50% ± 10%
MIN TYP MAX UNIT
f_SYSTEM MHz
USCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(see Note ⁽¹⁾, Figure 8 and Figure 9)
f_USCI
PARAMETER
USCI input clock frequency
TEST CONDITIONS
SMCLK, ACLK
Duty cycle = 50% ± 10%
V_CC
MIN TYP MAX UNIT
f_SYSTEM MHz
1.8 V
55
PMMCOREV = 0
ns
3V
38
t_SU,MI
SOMI input data setup time
2.4 V
30
PMMCOREV = 3
ns
3V
25
1.8 V
0
PMMCOREV = 0
ns
3V
0
t_HD,MI
SOMI input data hold time
2.4 V
0
PMMCOREV = 3
ns
3V
0
t_VALID,MO SIMO output data valid time ⁽²⁾
UCLK edge to SIMO valid,
C_L = 20 pF, PMMCOREV = 0
UCLK edge to SIMO valid,
C_L = 20 pF, PMMCOREV = 3
1.8 V
3V
2.4 V
3V
20
ns
18
16
ns
15
1.8 V
-10
t_HD,MO
SIMO output data hold time ⁽³⁾
C_L = 20 pF, PMMCOREV = 0
3V
-8
2.4 V
-10
ns
C_L = 20 pF, PMMCOREV = 3
3V
-8
ns
(1) f_UCxCLK = 1/2t_LO/HI with t_LO/HI ≥ max(t_{VALID,MO(USCI)} + t_SU,SI(Slave), t_SU,MI(USCI) + t_{VALID,SO(Slave)}).
For the slave's parameters t_SU,SI(Slave) and t_{VALID,SO(Slave)} see the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in Figure 8 and Figure 9.
(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 8
and Figure 9.
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