DS90C032B Datasheet, PDF (6/16 Pages) National Semiconductor (TI) – LVDS Quad CMOS Differential Line Receiver

DS90C032B
SNLS052C – MARCH 1999 – REVISED APRIL 2013
APPLICATIONS INFORMATION
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LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as
is shown in Figure 6. This configuration provides a clean signaling environment for the quick edge rates of the
drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair
cable, a parallel pair cable, or simply PCB traces. Typically the characteristic impedance of the media is in the
range of 100Ω. A termination resistor of 100Ω should be selected to match the media, and is located as close to
the receiver input pins as possible. The termination resistor converts the current sourced by the driver into a
voltage that is detected by the receiver. Other configurations are possible such as a multi-receiver configuration,
but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as well as
ground shifting, noise margin limits, and total termination loading must be taken into account.
TheDS90C032B differential line receiver is capable of detecting signals as low as 100 mV, over a ±1V common-
mode range centered around +1.2V. This is related to the driver offset voltage which is typically +1.2V. The
driven signal is centered around this voltage and may shift ±1V around this center point. The ±1V shifting may be
the result of a ground potential difference between the driver's ground reference and the receiver's ground
reference, the common-mode effects of coupled noise, or a combination of the two. Both receiver input pins
should honor their specified operating input voltage range of 0V to +2.4V (measured from each pin to ground),
exceeding these limits may turn on the ESD protection circuitry which will clamp the bus voltages.
RECEIVER FAILSAFE
The LVDS receiver is a high gain, high speed device that amplifies a small differential signal (20mV) to CMOS
logic levels. Due to the high gain and tight threshold of the receiver, care should be taken to prevent noise from
appearing as a valid signal.
The receiver's internal failsafe circuitry is designed to source/sink a small amount of current, providing failsafe
protection (a stable known state of HIGH output voltage) for floating and terminated (100Ω) receiver inputs in low
noise environment (differential noise < 10mV).
1. Open Input Pins.
TheDS90C032B is a quad receiver device, and if an application requires only 1, 2, or 3 receivers, the unused
channel(s) inputs should be left OPEN. Do not tie unused receiver inputs to ground or any other voltages.
The input is biased by internal high value pull up and pull down resistors to set the output to a HIGH state.
This internal circuitry will ensure a HIGH, stable output state for open inputs.
2. Terminated Input. TheDS90C032B requires external failsafe biasing for terminated input failsafe.
Terminated input failsafe is the case of a receiver that has a 100Ω termination across its inputs and the
driver is in the following situations. Unplugged from the bus, or the driver output is in TRI-STATE or in power-
off condition. The use of external biasing resistors provide a small bias to set the differential input voltage
while the line is un-driven, and therefore the receiver output will be in HIGH state. If the driver is removed
from the bus but the cable is still present and floating, the unplugged cable can become a floating antenna
that can pick up noise. The LVDS receiver is designed to detect very small amplitude and width signals and
recover them to standard logic levels. Thus, if the cable picks up more than 10mV of differential noise, the
receiver may respond. To insure that any noise is seen as common-mode and not differential, a balanced
interconnect and twisted pair cables is recommended, as they help to ensure that noise is coupled common
to both lines and rejected by the receivers.
3. Operation in environment with greater than 10mV differential noise.
TI recommends external failsafe biasing on its LVDS receivers for a number of system level and signal
quality reasons. First, only an application that requires failsafe biasing needs to employ it. Second, the
amount of failsafe biasing is now an application design parameter and can be custom tailored for the specific
application. In applications in low noise environments, they may choose to use a very small bias if any. For
applications with less balanced interconnects and/or in high noise environments they may choose to boost
failsafe further. TI's "LVDS Owner’s Manual provides detailed calculations for selecting the proper failsafe
biasing resistors. Third, the common-mode voltage is biased by the resistors during the un-driven state. This
is selected to be close to the nominal driver offset voltage (V_OS). Thus when switching between driven and
un-driven states, the common-mode modulation on the bus is held to a minimum.
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