DS90C032B Datasheet, PDF (4/16 Pages) National Semiconductor (TI) – LVDS Quad CMOS Differential Line Receiver

DS90C032B
SNLS052C – MARCH 1999 – REVISED APRIL 2013
Switching Characteristics
V_CC = +5.0V ± 10%, T_A = −40°C to +85°C^(1)(2)(3)
Symbol
Parameter
t_PHLD
t_PLHD
t_SKD
t_SK1
t_SK2
t_TLH
t_THL
t_PHZ
t_PLZ
t_PZH
t_PZL
Differential Propagation Delay High to Low
Differential Propagation Delay Low to High
Differential Skew |t_PHLD − t_PLHD|
Channel-to-Channel Skew⁽⁴⁾
Chip to Chip Skew⁽⁵⁾
Rise Time
Fall Time
Disable Time High to Z
Disable Time Low to Z
Enable Time Z to High
Enable Time Z to Low
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Conditions
C_L = 5 pF, V_ID = 200 mV,
See Figure 2 and Figure 3
R_L = 2 kΩ, C_L = 10 pF,
See Figure 4 and Figure 5
Min Typ Max Units
1.0 3.40 6.0 ns
1.0 3.48 6.0 ns
0 0.08 1.2 ns
0
0.6 1.5 ns
5.0 ns
0.5 2.5 ns
0.5 2.5 ns
10
20
ns
10
20
ns
4
15
ns
4
15
ns
(1) All typicals are given for: V_CC = +5.0V, T_A = +25°C.
(2) Generator waveform for all tests unless otherwise specified: f = 1 MHz, Z_O = 50Ω, t_r and t_f (0%–100%) ≤ 1 ns for R_IN and t_r and t_f ≤ 6 ns
for EN or EN*.
(3) C_L includes probe and jig capacitance.
(4) Channel-to-Channel Skew is defined as the difference between the propagation delay of one channel and that of the others on the same
chip with an event on the inputs.
(5) Chip to Chip Skew is defined as the difference between the minimum and maximum specified differential propagation delays.
Parameter Measurement Information
Figure 2. Receiver Propagation Delay and Transition Time Test Circuit
Figure 3. Receiver Propagation Delay and Transition Time Waveforms
4
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