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DS64EV400_15 Datasheet, PDF (6/22 Pages) Texas Instruments – Programmable Quad Equalizer
DS64EV400
SNLS281H – AUGUST 2007 – REVISED APRIL 2013
Electrical Characteristics — Serial Management Bus Interface
Over recommended operating supply and temperature ranges unless other specified.
Parameter
Test Conditions
SERIAL BUS INTERFACE DC SPECIFICATIONS
VIL
VIH
IPULLUP
Data, Clock Input Low Voltage
Data, Clock Input High Voltage
Current Through Pull-Up Resistor or
Current Source
High Power Specification
VDD
ILEAK-Bus
ILEAK-Pin
CI
RTERM
Nominal Bus Voltage
Input Leakage Per Bus Segment
Input Leakage Per Device Pin
Capacitance for SDA and SDC
External Termination Resistance pull
to VDD = 2.5V ± 5% OR
3.3V ± 10%
See (1)
See (1) (2)
VDD3.3, (1) (2) (3)
VDD2.5, (1) (2) (3)
SERIAL BUS INTERFACE TIMING SPECIFICATIONS (Figure 8)
FSMB
Bus Operating Frequency
See (4)
TBUF
Bus Free Time Between Stop and
Start Condition
THD:STA
Hold time after (Repeated) Start
Condition. After this period, the first
clock is generated.
At IPULLUP, Max
TSU:STA Repeated Start Condition Setup Time
TSU:STO Stop Condition Setup Time
THD:DAT Data Hold Time
TSU:DAT
TTIMEOUT
TLOW
THIGH
TLOW:SEXT
tF
tR
tPOR
Data Setup Time
Detect Clock Low Timeout
Clock Low Period
Clock High Period
Cumulative Clock Low Extend Time
(Slave Device)
Clock/Data Fall Time
Clock/Data Rise Time
Time in which a device must be
operational after power-on reset
See (4)
See (4)
See (4)
See (4)
See (4)
See (4)
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Min Typ Max Units
0.8
V
2.1
VDD
V
4
mA
2.375
3.6
V
-200
+200
µA
-15
µA
10
pF
2000
Ω
1000
Ω
10
100
kHz
4.7
µs
4.0
µs
4.7
µs
4.0
µs
300
ns
250
ns
25
35
ms
4.7
µs
4.0
50
µs
2
ms
300
ns
1000
ns
500
ms
(1) Recommended value. Parameter not tested in production.
(2) Recommended maximum capacitance load per bus segment is 400pF.
(3) Maximum termination voltage should be identical to the device supply voltage.
(4) Compliant to SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1
SMBus common AC specifications for details.
6
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