DS64EV400_15 Datasheet, PDF (13/22 Pages) Texas Instruments – Programmable Quad Equalizer

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DS64EV400 Applications Information
DS64EV400
SNLS281H – AUGUST 2007 – REVISED APRIL 2013
IN_n r
Equalizer
Limiting
Amplifier
Signal Detect
CML
Driver
OUT_n r
ENn
Reg 07 = K¶00
(Default)
SDn
Figure 10. Automatic Enable Configuration
UNUSED EQUALIZER CHANNELS
It is recommended to put all unused channels into standby mode.
GENERAL RECOMMENDATIONS
The DS64EV400 is a high performance circuit capable of delivering excellent performance. Careful attention
must be paid to the details associated with high-speed design as well as providing a clean power supply. Refer
to the LVDS Owner's Manual for more detailed information on high speed design tips to address signal integrity
design issues.
PCB LAYOUT CONSIDERATIONS FOR DIFFERENTIAL PAIRS
The CML inputs and outputs must have a controlled differential impedance of 100Ω. It is preferable to route CML
lines exclusively on one layer of the board, particularly for the input traces. The use of vias should be avoided if
possible. If vias must be used, they should be used sparingly and must be placed symmetrically for each side of
a given differential pair. Route the CML signals away from other signals and noise sources on the printed circuit
board. See AN-1187(SNOA401) for additional information on WQFN packages.
POWER SUPPLY BYPASSING
Two approaches are recommended to ensure that the DS64EV400 is provided with an adequate power supply.
First, the supply (V_DD) and ground (GND) pins should be connected to power planes routed on adjacent layers of
the printed circuit board. The layer thickness of the dielectric should be minimized so that the V_DD and GND
planes create a low inductance supply with distributed capacitance. Second, careful attention to supply
bypassing through the proper use of bypass capacitors is required. A 0.01μF bypass capacitor should be
connected to each V_DD pin such that the capacitor is placed as close as possible to the DS64EV400. Smaller
body size capacitors can help facilitate proper component placement. Additionally, three capacitors with
capacitance in the range of 2.2 μF to 10 μF should be incorporated in the power supply bypassing design as
well. These capacitors can be either tantalum or an ultra-low ESR ceramic and should be placed as close as
possible to the DS64EV400.
DC COUPLING
The DS64EV400 supports both AC coupling with external ac coupling capacitor, and DC coupling to its upstream
driver, or downstream receiver. With DC coupling, users must ensure the input signal common mode is within the
range of the electrical specification V_ICMDC and the device output is terminated with 50 Ω to V_DD. When power-up
and power-down the device, both the DS64EV400 and the downstream receiver should be power-up and power-
down together. This is to avoid the internal ESD structures at the output of the DS64EV400 at power-down from
being turned on by the downstream receiver.
Copyright © 2007–2013, Texas Instruments Incorporated
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