DS64EV400_15 Datasheet, PDF (12/22 Pages) Texas Instruments – Programmable Quad Equalizer

DS64EV400
SNLS281H – AUGUST 2007 – REVISED APRIL 2013
Register 07[0] (SMBus)
0 : Disable
0 : Disable
1 : Enable
1 : Enable
Table 3. Controlling Device State
ENn Pin (CMOS)
1
0
X
X
CH 0:
Reg. 03 bit 3
CH 1:
Reg. 03 bit 7
CH 2:
Reg. 04 bit 3
CH 3:
Reg. 04 bit 7
(EN Control)
X
X
0
1
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Device State
ACTIVE
STANDBY
ACTIVE
STANDBY
SIGNAL DETECT
The DS64EV400 features a signal detect circuit on each data channel. The status of the signal of each channel
can be determined by either reading the Signal Detect bit (SDn) in the SMBus registers (see Table 1) or by the
state of each SDn pin. An output logic high indicates the presence of a signal that has exceeded the ON
threshold value (called SD_ON). An output logic Low means that the input signal has fallen below the OFF
threshold value (called SD_OFF). These values are programmed via the SMBus (Table 1). If not programmed via
the SMBus, the thresholds take on the default values as shown in Table 4. The Signal Detect threshold values
can be changed through the SMBus. All threshold values specified are DC peak-to-peak differential signals
(positive signal minus negative signal) at the input of the device.
Channel 0: Bit 1
Channel 1: Bit 3
Channel 2: Bit 5
Channel 3: Bit 7
0
0
1
1
Table 4. Signal Detect Threshold Values
Channel 0: Bit 0
Channel 1: Bit 2
Channel 2: Bit 4
Channel 3: Bit 6
0
1
0
1
SD_OFF Threshold
Register 06 (mV)
40 (Default)
30
55
45
SD_ON Threshold
Register 05 (mV)
70 (Default)
55
90
75
OUTPUT LEVEL CONTROL
The output amplitude of the CML drivers for each channel can be controlled via the SMBus (see Table 1). The
default output level is 620 mV_p-p. The following Table presents the output level values supported:
All Channels : Bit 3
0
0
1
1
Table 5. Output Level Control Settings
All Channels : Bit 2
0
1
0
1
Output Level Register 08 (mV_P-P)
400
540
620 (Default)
760
AUTOMATIC ENABLE FEATURE
It may be desirable to place unused channels in power-saving Standby mode. This can be accomplished by
connecting the Signal detect (SDn) pin to the Enable (ENn) pin for each channel (See Figure 10). In order for this
option to function properly, the register value for Reg. 07 should be 00'h (default value). If an input signal swing
applied to a data channel is above the voltage level threshold as shown in Table 4, then the SDn output pin is
asserted High. If the SDn pin is connected to the ENn pin, this will enable the equalizer, limiting amplifier, and
output buffer on the data channels; thus the DS64EV400 will automatically enter the ACTIVE state. If the input
signal swing falls below the SD_OFF threshold level, then the SDn output will be asserted Low, causing the
channel to be placed in the STANDBY state.
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