DS64EV400_15 Datasheet, PDF (5/22 Pages) Texas Instruments – Programmable Quad Equalizer

DS64EV400
www.ti.com
SNLS281H – AUGUST 2007 – REVISED APRIL 2013
Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges with default register settings unless other specified.
Parameter
Test Conditions
Min Typ ⁽¹⁾ Max
R_IN
Input Resistance
CML OUTPUTS (OUT_n+, OUT_n-)
Differential across IN+ and IN-, Figure 7
85
100 115
V_OD
Output Differential Voltage Level
Differential measurement with OUT+ and OUT-
(OUT diff)
terminated by 50Ω to GND, AC-Coupled
500
620 725
Figure 3
V_OCM
Output Common Mode Voltage
Single-ended measurement DC-Coupled with
50Ω terminations⁽⁵⁾
V_DD–
0.2
V_DD–
0.1
t_R, t_F
Transition Time
20% to 80% of differential output voltage,
measured within 1” from output pins.
20
60
Figure 3,⁽⁵⁾
R_O
Output Resistance
Single ended to V_DD
42
50
58
R_LO
Differential Output Return Loss
100 MHz – 1.6 GHz, with fixture’s effect de-
embedded. IN+ = static high.
10
t_PLHD
Differential Low to High Propagation Propagation delay measurement at 50% VO
Delay
between input to output, 100 Mbps. Figure 4,
240
(5)
t_PHLD
Differential High to Low Propagation
Delay
240
t_CCSK
Inter Pair Channel to Channel Skew Difference in 50% crossing between channels
7
t_PPSK
Part to Part Output Skew
Difference in 50% crossing between outputs
20
EQUALIZATION
DJ1
Residual Deterministic Jitter
at 10 Gbps
30” of 6 mil microstrip FR4,
EQ Setting 0x06, PRBS-7 (2⁷-1) pattern.⁽⁶⁾
0.20
DJ2
Residual Deterministic Jitter
at 6.4 Gbps
40” of 6 mil microstrip FR4,
EQ Setting 0x06, PRBS-7 (2⁷-1) pattern.⁽⁷⁾⁽⁶⁾
0.17 0.26
DJ3
Residual Deterministic Jitter
at 5 Gbps
40” of 6 mil microstrip FR4,
EQ Setting 0x07, PRBS-7 (2⁷-1) pattern.^{(7) (6)}
0.12 0.20
DJ4
Residual Deterministic Jitter
at 2.5 Gbps
RJ
Random Jitter
40” of 6 mil microstrip FR4,
EQ Setting 0x07, PRBS-7 (2⁷-1) pattern.⁽⁷⁾⁽⁶⁾
See ^{(8) (9)}
0.1 0.16
0.5
SIGNAL DETECT and ENABLE TIMING
t_ZISD
Input OFF to ON detect — SD Output Response time measurement at V_IN to SD
High Response Time
output, V_IN = 800 mV_P-P, 100 Mbps, 40” of 6 mil
35
t_IZSD
Input ON to OFF detect — SD Output
Low Response Time
microstrip FR4
Figure 2 and Figure 5,⁽⁸⁾
400
t_OZOED
EN High to Output ON Response
Time
Response time measurement at EN input to
V_O, V_IN = 800 mV_P-P, 100 Mbps, 40” of 6 mil
150
t_ZOED
EN Low to Output OFF Response
Time
microstrip FR4
Figure 2 and Figure 7, ⁽⁸⁾
5
Units
Ω
mV_P-P
V
ps
Ω
dB
ps
ps
ps
ps
UI_P-P
UI_P-P
UI_P-P
UI_P-P
psrms
ns
ns
ns
ns
(6) Deterministic jitter is measured at the differential outputs (point C of Figure 2), minus the deterministic jitter before the test channel (point
A of Figure 2). Random jitter is removed through the use of averaging or similar means.
(7) Specification is ensured by characterization at optimal boost setting and is not tested in production.
(8) Measured with clock-like {11111 00000} pattern.
(9) Random jitter contributed by the equalizer is defined as sqrt (J_OUT2 – J_IN2). J_OUT is the random jitter at equalizer outputs in ps-rms, see
point C of Figure 2; J_IN is the random jitter at the input of the equalizer in ps-rms, see point B of Figure 2.
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