DS64EV400_15 Datasheet, PDF (2/22 Pages) Texas Instruments – Programmable Quad Equalizer

DS64EV400
SNLS281H – AUGUST 2007 – REVISED APRIL 2013
www.ti.com
Pin Descriptions
Pin Name Pin No. I/O, Type⁽¹⁾
Description
HIGH SPEED DIFFERENTIAL I/O
IN_0+
IN_0–
1
I, CML
Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100Ω
2
terminating resistor is connected between IN_0+ and IN_0-. Refer to Figure 7.
IN_1+
IN_1–
4
I, CML
Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100Ω
5
terminating resistor is connected between IN_1+ and IN_1-. Refer to Figure 7.
IN_2+
IN_2–
8
I, CML
Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100Ω
9
terminating resistor is connected between IN_2+ and IN_2-. Refer to Figure 7.
IN_3+
IN_3–
11
I, CML
Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100Ω
12
terminating resistor is connected between IN_3+ and IN_3-. Refer to Figure 7.
OUT_0+
OUT_0–
36
O, CML
35
OUT_1+
OUT_1–
33
O, CML
32
OUT_2+
OUT_2–
29
O, CML
28
OUT_3+
OUT_3–
26
O, CML
25
EQUALIZATION CONTROL
Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50Ω
terminating resistor connects OUT_0+ to V_DD and OUT_0- to V_DD.
Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50Ω
terminating resistor connects OUT_1+ to V_DD and OUT_1- to V_DD.
Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50Ω
terminating resistor connects OUT_2+ to V_DD and OUT_2- to V_DD.
Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50Ω
terminating resistor connects OUT_3+ to V_DD and OUT_3- to V_DD.
BST_2
BST_1
BST_0
37
I, LVCMOS BST_2, BST_1, and BST_0 select the equalizer strength for all EQ channels. BST_2 is
14
internally pulled high. BST_1 and BST_0 are internally pulled low.
23
DEVICE CONTROL
EN0
44
I, LVCMOS Enable Equalizer Channel 0 input. When held High, normal operation is selected. When held
Low, standby mode is selected. EN is internally pulled High.
EN1
42
I, LVCMOS Enable Equalizer Channel 1 input. When held High, normal operation is selected. When held
Low, standby mode is selected. EN is internally pulled High.
EN2
40
I, LVCMOS Enable Equalizer Channel 2 input. When held High, normal operation is selected. When held
Low, standby mode is selected. EN is internally pulled High.
EN3
38
I, LVCMOS Enable Equalizer Channel 3 input. When held High, normal operation is selected. When held
Low, standby mode is selected. EN is internally pulled High.
FEB
21
I, LVCMOS Force External Boost. When held high, the equalizer boost setting is controlled by BST_[2:0]
pins. When held low, the equalizer boost setting is controlled by SMBus (Table 1) register bits.
FEB is internally pulled High.
SD0
45
O, LVCMOS Equalizer Ch0 Signal Detect Output. Produces a High when signal is detected.
SD1
43
O, LVCMOS Equalizer Ch1 Signal Detect Output. Produces a High when signal is detected.
SD2
41
O, LVCMOS Equalizer Ch2 Signal Detect Output. Produces a High when signal is detected.
SD3
39
O, LVCMOS Equalizer Ch3 Signal Detect Output. Produces a High when signal is detected.
POWER
V_DD
3, 6, 7,
Power
V_DD = 2.5V ± 5% or 3.3V ± 10%. V_DD pins should be tied to V_DD plane through low inductance
10, 13,
path. A 0.01μF bypass capacitor should be connected between each V_DD pin to GND planes.
15, 46
GND
22, 24,
27, 30,
31, 34
Power
Ground reference. GND should be tied to a solid ground plane through a low impedance path.
DAP
PAD
Power
Ground reference. The exposed pad at the center of the package must be connected to ground
plane of the board.
SERIAL MANAGEMENT BUS (SMBus) INTERFACE CONTROL PINS
SDA
SDC
CS
18
I/O, LVCMOS Data input/output (bi-directional). Internally pulled high.
17
I, LVCMOS Clock input. Internally pulled high.
16
I, LVCMOS Chip select. When pulled high, access to the equalizer SMBus registers are enabled. When
pulled low, access to the equalizer SMBus registers are disabled. Please refer to “ SMBus
configuration Registers” section for detail information.
Other
Reserv
19, 20
47,48
Reserved. Do not connect.
(1) Note: I = Input O = Output
2
Submit Documentation Feedback
Product Folder Links: DS64EV400
Copyright © 2007–2013, Texas Instruments Incorporated