DS100BR410_14 Datasheet, PDF (6/23 Pages) Texas Instruments – Low Power Quad Channel Repeater with 10.3125 Gbps Equalizer and De-Emphasis Driver

DS100BR410
SNLS326B – OCTOBER 2010 – REVISED APRIL 2013
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Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges with default register settings unless other specified. ⁽¹⁾
Parameter
Test Conditions
Min
Typ
Max
Units
Equalization
DJ1
Residual Deterministic Jitter
V_TX = 1.0 V_P-P,
at 10.3125 Gbps
12 meter 30 AWG cable,
EQ = 03F'h (BST[2:0] = 111),
PRBS-7 (2⁷-1) pattern. ⁽⁷⁾
0.10
0.22
UI_P-P
DJ2
Residual Deterministic Jitter
V_TX = 1.0 V_P-P,
at 6.0 Gbps
12 meter 30 AWG cable,
EQ = 07F'h, PRBS-7 (2⁷-1) pattern.
(7)
0.07
0.12
UI_P-P
Signal DETECT and ENABLE Timing
t_ZISD
Input OFF to ON detect — SD
Output High Response Time
Response time measurement at
V_IN to SD output, V_IN = 800 mV_P-P,
35
ns
t_IZSD
Input ON to OFF detect — SD
Output Low Response Time
100 Mbps, 40” of 6 mil microstrip
FR4. Figure 4
400
ns
t_OZOED
EN High to Output ON Response
Time
Response time measurement at
EN input to V_O, V_IN = 800 mV_P-P,
150
ns
t_ZOED
EN Low to Output OFF Response
Time
100 Mbps, 40” of 6 mil microstrip
FR4. Figure 5
5
ns
(7) Deterministic jitter is measured at the differential outputs (point C of Figure 1), minus the deterministic jitter before the test channel (point
A of Figure 1). Random jitter is removed through the use of averaging or similar means.
Electrical Characteristics — Serial Management Bus Interface
Over recommended operating supply and temperature ranges unless other specified. ⁽¹⁾
Parameter
Test Conditions
Min
Serial Bus Interface DC Specifications
V_IL
Data, Clock Input Low Voltage
V_IH
Data, Clock Input High Voltage
2.1
I_PULLUP
Current Through Pull-Up Resistor High Power Specification
or Current Source
4
V_DD
I_LEAK-Bus
Nominal Bus Voltage
Input Leakage Per Bus Segment
See ⁽²⁾
I_LEAK-Pin
C_I
R_TERM
Input Leakage Per Device Pin
Capacitance for SDA and SDC
External Termination Resistance
pull to V_DD = 2.5V ± 5% OR 3.3V ±
10%
See ^{(2) (3)}
V_DD3.3, ^{(2) (3)}
V_DD2.5, ^{(2) (3)}
Serial Bus Interface Timing Specifications – (See Figure 6) ⁽⁴⁾⁽⁵⁾
2.375
-200
F_SMB
Bus Operating Frequency
10
T_BUF
Bus Free Time Between Stop and
Start Condition
4.7
T_HD:STA
Hold time after (Repeated) Start
At I_PULLUP, Max
Condition. After this period, the first
4.0
clock is generated.
T_SU:STA
Repeated Start Condition Setup
Time
4.7
T_SU:STO
Stop Condition Setup Time
4.0
T_HD:DAT
Data Hold Time
300
Typ
-15
2000
1000
Max
0.8
V_DD
3.6
+200
10
100
Units
V
V
mA
V
µA
µA
pF
Ω
Ω
kHz
µs
µs
µs
µs
ns
(1) Typical values represent most likely parametric norms at V_DD = 2.5V, T_A = 25°C., and at the Recommended Operation Conditions at the
time of product characterization and are not ensured.
(2) Maximum termination voltage should be identical to the device supply voltage.
(3) Compliant to SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1
SMBus common AC specifications for details.
(4) Recommended value. Parameter not tested in production.
(5) Recommended maximum capacitance load per bus segment is 400pF.
6
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