DS100BR410_14 Datasheet, PDF (5/23 Pages) Texas Instruments – Low Power Quad Channel Repeater with 10.3125 Gbps Equalizer and De-Emphasis Driver

DS100BR410
www.ti.com
SNLS326B – OCTOBER 2010 – REVISED APRIL 2013
Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges with default register settings unless other specified. ⁽¹⁾
Parameter
Test Conditions
Min
Typ
Max
Units
I_IN-P
Input Leakage Current with Internal V_IN = V_DD, with internal pull-down
Pull-Down/Up Resistors
resistors
+65
μA
V_IN = GND, with internal pull-up
-50
μA
resistors
Signal Detect
SDH
Signal Detect ON Threshold Level Default input signal level to assert
130
SD pin, 10.3125 Gbps
mV_p-p
SDL
Signal Detect OFF Threshold Level Default input signal level to de-
assert SD, 10.3125 Gbps
60
mV_p-p
CML Receiver Inputs (IN_n+, IN_n-)
V_TX
Source Transmit Launch Signal
AC-Coupled Requirement,
Level (IN diff)
Differential measurement at point
600
A. Figure 1
1600
mV_P-P
R_LI
Differential Input Return Loss -
100 MHz – 6 GHz, with fixture’s
SDD11
effect de-embedded
-15
dB
CML Driver Outputs (OUT_n+, OUT_n-)
V_OD
Output Differential Voltage Level⁽³⁾,
Figure 2
Differential measurement with
OUT+ and OUT- terminated by
50Ω to GND, AC-Coupled,
VOD_SEL = open (1.0 Vp-p),
DE_SEL = GND
750
970
1150
mV_P-P
V_{OD_DE}
De-Emphasis Levels^{(4) (5)}
t_R, t_F
Transition Time
Differential measurement with
OUT+ and OUT- terminated by
50Ω to GND, AC-Coupled,
VOD_SEL = V_DD (1.2 Vp-p),
DE_SEL = GND
1140
mV_P-P
DE_SEL = 20kΩ to GND,
VOD_SEL = V_DD (1.2 Vp-p)
-3
dB
DE_SEL = open,
VOD_SEL = V_DD (1.2 Vp-p)
-6
dB
DE_SEL = V_DD,
VOD_SEL = V_DD (1.2 Vp-p)
-9
dB
20% to 80% of differential output
voltage, measured within 1” from
30
38
45
ps
output pins. Figure 2
R_LO
Differential Output Return Loss - 100 MHz – 6 GHz, with fixture’s
SDD22
effect de-embedded. IN+ = static
-15
dB
high.
t_PLHD
Differential Low to High
Propagation Delay
Propagation delay measurement at
50% crossing between input to
240
ps
t_PHLD
Differential High to Low
Propagation Delay
output, 100 Mbps. Figure 3
240
ps
t_CCSK
Inter Pair Channel to Channel
Skew
Difference in 50% crossing
between channels
7
ps
t_PPSK
Part to Part Output Skew
Difference in 50% crossing
between outputs
20
ps
RJ
Random Jitter
V_TX = 1.0 Vp-p, BST_[2:0] = 000,
(4) (6)
0.3
ps_rms
(3) Measured with clock-like {11111 00000} pattern.
(4) Measured with clock-like {11111 00000} pattern.
(5) The de-emphasis level of −3 dB, −6 dB, −9 dB are for V_OD = 1.2 Vp-p. At lower V_OD level, the de-emphasis levels are reduced.
(6) Random jitter contributed by the equalizer is defined as sqrt (J_OUT2 – J_IN2). J_OUT is the random jitter at equalizer outputs in ps-rms, see
point C of Figure 1; J_IN is the random jitter at the input of the equalizer in ps-rms, see point B of Figure 1.
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