DS100BR410_14 Datasheet, PDF (10/23 Pages) Texas Instruments – Low Power Quad Channel Repeater with 10.3125 Gbps Equalizer and De-Emphasis Driver

DS100BR410
SNLS326B – OCTOBER 2010 – REVISED APRIL 2013
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SIGNAL DETECT
The DS100BR410 features a signal detect circuit on each data channel. The status of the signal of each channel
can be determined by either reading the Signal Detect bit (SDn) in the SMBus registers (see Table 4) or by the
state of each SDn pin. An output logic high indicates the presence of a signal that has exceeded the ON
threshold value (called SDH). An output logic Low means that the input signal has fallen below the OFF
threshold value (called SDL). These values are programmed via the SMBus. If not programmed via the SMBus,
the thresholds take on the default values. The Signal Detect threshold values can be changed through the
SMBus. All threshold values specified are DC peak-to-peak differential signals (positive signal minus negative
signal) at the input of the device.
OUTPUT LEVEL CONTROL
The output amplitude of the CML drivers can be controlled via the 4–level analog input VOD_SEL pin or via
SMBus (see Table 4). The default V_OD level is 1.0 Vp-p.
Tie High - V_DD
Open* (default)
20 kΩ resistor to GND
Tie to GND
Table 2. VOD_SEL Pin Configuration
VOD_SEL Pin
Result
1.2 Vp-p
1.0 Vp-p
800 mVp-p
600 mVp-p
OUTPUT DE-EMPHASIS CONTROL
The output De-Emphasis may be controled via the 4–level analog input DE_SEL pin or via SMBus (see Table 4).
Tie High - V_DD
Open* (default)
20 kΩ resistor to GND
Tie to GND
DE_SEL Pin
Table 3. DE_SEL Pin Configuration
Result
-9 dB
-6 dB
-3 dB
0 dB
AUTOMATIC ENABLE FEATURE
It may be desirable to place unused channels in power-saving Standby mode. This can be accomplished by
connecting the Signal detect (SDn) pin to the Enable (ENn) pin for each channel (See Figure 7).
System Management Bus (SMBus) and Configuration Registers
The System Management Bus interface is compatible to SMBus 2.0 physical layer specification. The use of the
Chip Select signal is required. Holding the CS pin High enables the SMBus port allowing access to the
configuration registers. Holding the CS pin Low disables the device's SMBus allowing communication from the
host to other slave devices on the bus. In the STANDBY state, the System Management Bus remains active.
When communication to other devices on the SMBus is active, the CS signal for the DS100BR410s must be
driven Low.
The address byte for all DS100BR410s is AC'h. Based on the SMBus 2.0 specification, the DS100BR410 has a
7-bit slave address of 1010110'b. The LSB is set to 0'b (for a WRITE), thus the 8-bit value is 1010 1100'b or
AC'h.
The SDA, SDC and CS pins are 3.3V tolerant, but are not 5V tolerant. External pull-up resistor is required on the
SDA. The resistor value can be from 1 kΩ to 5 kΩ depending on the voltage, loading and speed. The SDC and
CS may also require an external pull-up resistor and it depends on the Host that drives the bus.
Transfer of Data via the SMBus
During normal operation the data on SDA must be stable during the time when SDC is High.
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