DS100BR410_14 Datasheet, PDF (2/23 Pages) Texas Instruments – Low Power Quad Channel Repeater with 10.3125 Gbps Equalizer and De-Emphasis Driver

DS100BR410
SNLS326B – OCTOBER 2010 – REVISED APRIL 2013
Connection Diagram
IN_0+ 1
IN_0- 2
V_DD 3
IN_1+ 4
IN_1- 5
V_DD 6
V_DD 7
IN_2+ 8
IN_2- 9
V_DD 10
IN_3+ 11
IN_3- 12
DS100BR410
TOP VIEW
DAP = GND
36 OUT_0+
35 OUT_0-
34 GND
33 OUT_1+
32 OUT_1-
31 GND
30 GND
29 OUT_2+
28 OUT_2-
27 GND
26 OUT_3+
25 OUT_3-
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Pin Name
Pin #
I/O, Type⁽¹⁾
HIGH SPEED DIFFERENTIAL I/O
IN_0+
IN_0–
1
I, CML
2
IN_1+
IN_1–
4
I, CML
5
IN_2+
IN_2–
8
I, CML
9
IN_3+
IN_3–
11
I, CML
12
OUT_0+
OUT_0–
36
O, CML
35
OUT_1+
OUT_1–
33
O, CML
32
OUT_2+
OUT_2–
29
O, CML
28
OUT_3+
OUT_3–
26
O, CML
25
2.5V LVCMOS CONTROL PINS
BST_2
BST_1
BST_0
37
I, LVCMOS
14
23
EN0
44
I, LVCMOS
EN1
42
EN2
40
EN3
38
Pin Descriptions
Description
Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100Ω
terminating resistor connects IN_0+ to IN_0-.
Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100Ω
terminating resistor connects IN_1+ to IN_1-.
Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100Ω
terminating resistor connects IN_2+ to IN_2-.
Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100Ω
terminating resistor connects IN_3+ to IN_3-.
Inverting and non-inverting CML differential outputs from the driver. An on-chip 100Ω
terminating resistor connects OUT_0+ to OUT_0-.
Inverting and non-inverting CML differential outputs from the driver. An on-chip 100Ω
terminating resistor connects OUT_1+ to OUT_1-.
Inverting and non-inverting CML differential outputs from the driver. An on-chip 100Ω
terminating resistor connects OUT_2+ to OUT_2-.
Inverting and non-inverting CML differential outputs from the driver. An on-chip 100Ω
terminating resistor connects OUT_3+ to OUT_3-.
BST_2, BST_1, and BST_0 select the equalizer boost level for all channels.
BST_2 and BST_1 are internally pulled high.
BST_0 is internally pulled low. See Table 1
Enable channel n input.
When held High, normal operation is selected.
When held Low, standby mode is selected.
EN is internally pulled High.
(1) Note: I = Input O = Output, LVCMOS pins are 2.5 V levels only, only SMBus pins SDA, SDC and CS are 3.3V tolerant.
2
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