DS100BR410_14 Datasheet, PDF (14/23 Pages) Texas Instruments – Low Power Quad Channel Repeater with 10.3125 Gbps Equalizer and De-Emphasis Driver

DS100BR410
SNLS326B – OCTOBER 2010 – REVISED APRIL 2013
ADD
(hex)
19
REG Name
Channel 0
EN and EQ
Control
1A
EQ Control
Channel 0
Table 4. DS100BR410 Register Map (continued)
Bit(s)
Field
7:5
Reserved
4
Channel Enable
3:1
Reserved
0
Boost[8]
7:0
Boost[7:0]
Type
R/W
R/W
Default
(binary)
000
1
R/W 000
R/W 0
R/W 00000000
0 = Disabled
1 = Enabled
See Table 5
See Table 5
Description
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bit[8]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
bit[7]
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
Table 5. Boost / EQ SMBus Register: 16 levels - recommended settings
bit[6]
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
1
Boost Register Bits
bit[5] bit[4] bit[3]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
1
0
1
0
0
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
bit[2]
0
0
0
0
1
1
0
1
1
1
1
1
0
1
1
1
bit[1]
0
0
1
1
1
0
1
1
0
1
1
1
1
1
1
1
bit[0]
0
1
0
1
1
1
1
1
1
1
1
1
0
1
1
1
Result
@ 5.5 GHz
000'h - 2.7 dB (BST_[2:0]=000)
001'h - 7.3 dB (BST_[2:0]=001)
002'h - 10.3 dB
003'h - 12.2 dB (BST_[2:0]=010)
007'h - 16.6 dB (BST_[2:0]=011)
015'h - 17 dB
00B'h - 19.2 dB
00F'h - 20.6 dB (BST_[2:0]=100)
055'h - 21.9 dB
01F'h - 24.8 dB (BST_[2:0]=101)
02F'h - 27.6 dB (BST_[2:0]=110)
03F'h - 28.9 dB (BST_[2:0]=111)
0AA'h - 31.3 dB
07F'h - 33.3 dB
0BF'h - 35.7 dB
0FF'h - 37 dB
Applications Information
GENERAL RECOMMENDATIONS
The DS100BR410 is a high performance circuit capable of delivering excellent performance up to 10.3125 Gbps.
Careful attention must be paid to the details associated with high-speed design as well as providing a clean
power supply. Refer to the LVDS Owner's Manual for more detailed information on high speed design tips to
address signal integrity design issues.
UNUSED CHANNEL
It is recommended to disable the unused channel (EN[3:0] = LOW). The power consumption of the device is
reduced when the channel is disabled.
PCB LAYOUT CONSIDERATIONS FOR DIFFERENTIAL PAIRS
The high speed CML inputs and outputs must have a controlled differential impedance of 100Ω. It is preferable to
route differential lines exclusively on one layer of the board, particularly for the input traces. The use of vias
should be avoided if possible. If vias must be used, they should be used sparingly and must be placed
symmetrically for each side of a given differential pair. Route the differential signals away from other signals and
noise sources on the printed circuit board. See AN-1187 (SNOA401) for additional information on WQFN
packages.
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