DS100BR410_14 Datasheet, PDF (3/23 Pages) Texas Instruments – Low Power Quad Channel Repeater with 10.3125 Gbps Equalizer and De-Emphasis Driver

DS100BR410
www.ti.com
SNLS326B – OCTOBER 2010 – REVISED APRIL 2013
Pin Descriptions (continued)
Pin Name
Pin #
I/O, Type⁽¹⁾
Description
PIN_MODE
21
I, LVCMOS Pin mode control input.
When held High, device is in Pin control mode.
When held Low, device is in SMBus Control Mode
PIN_MODE is internally pulled High.
SD0
45
O, LVCMOS Signal detect n output.
SD1
43
Output is High when signal is detected.
SD2
41
Output is Low when signal is NOT detected.
SD3
39
OOB_DIS
47
I, LVCMOS OOB disable control input.
When held High, OOB is disabled.
When held Low, OOB is enabled.
Out Of Band (OOB) for SATA/SAS applications is active.
OOB_DIS is internally pulled Low.
Analog Input Pins (4–level Inputs)
VOD_SEL
19
I, analog Differential Output Voltage Select Input
Tie to V_DD, V_OD = 1.2 Vp-p
Leave Open, V_OD = 1.0 Vp-p
Resistor (20 kΩ) to GND, V_OD = 800 mVp-p
Tie to GND, V_OD = 600 mVp-p
DE_SEL
20
I, analog De-Emphasis Select Input
Tie to V_DD = -9 dB
Leave Open = -6 dB
Resistor (20 kΩ) to GND = -3 dB
Tie to GND = 0 dB
SERIAL MANAGEMENT BUS (SMBus) INTERFACE
SDA
18
I/O, LVCMOS Data Input / Open Drain Output
External pull-up resistor is required.
Pin is 3.3 V LVCMOS tolerant.
SDC
17
I, LVCMOS Clock Input
Pin is 3.3 V LVCMOS tolerant.
CS
16
I, LVCMOS Chip Select
When high, access to the SMBus registers are enabled. When low, access to the SMBus
registers are disabled. Please refer to “SMBus configuration Registers” section for detail
information.
Pin is 3.3 V LVCMOS tolerant.
POWER
V_DD
3, 6, 7,
Power
V_DD = 2.5 V ± 5%
10, 13,
15, 46
GND
22, 24,
27, 30,
31, 34
Power
Ground reference.
DAP
PAD
Power
Ground reference. The exposed pad at the center of the package must be connected to ground
plane of the board with at least 4 via to lower the ground impedance and improve the thermal
performance of the package.
RES
48
NC
Reserved – Do not connect
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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