BQ24030-Q1 Datasheet, PDF (6/34 Pages) Texas Instruments – SINGLE-CHIP CHARGE AND SYSTEM POWER-PATH MANAGEMENT IC

bq24030-Q1
bq24031-Q1
SLUS793B – APRIL 2008 – REVISED OCTOBER 2009.................................................................................................................................................... www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
over junction temperature range (0°C ≤ T_J ≤ 125°C) and recommended supply voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
Charge Termination Detection
I_(TERM)
Charge termination
detection range
V_I(BAT) < V_(RCH), I_(TERM) = (K_(SET) × V_(TERM))/R_SET
10
150
V_(TERM-AC)
AC-charge termination
detection voltage,
measured on ISET1
V_I(BAT) > V_(RCH) , PSEL = high, ACPG = low
235
250
265
V_(TAPER-USB)
USB-charge termination
detection voltage,
measured on ISET1
V_I(BAT) > V_(RCH),
PSEL = low or PSEL = high and ACPG = high
95
100
130
T_DGL(TERM)
Deglitch time for
termination detection
Temperature Sense Comparators
t_FALL = 100 ns, 10-mV overdrive,
I_CHG increasing above or decreasing below threshold
22.5
V_LTF
V_HTF
I_TS
High voltage threshold
Low voltage threshold
Temperature sense current
source
Temperature fault at V(TS) > V_LTF
Temperature fault at V(TS) < V_HTF
2.465
0.485
94
2.500
0.500
100
2.535
0.515
106
T_DGL(TF)
Deglitch time for
temperature fault
detection ⁽¹⁴⁾
R_(TMR) = 50 kΩ, V_I(BAT) increasing or decreasing above
and below; 100-ns fall time, 10-mV overdrive
22.5
Battery Recharge Threshold
V_RCH
Recharge threshold
voltage
V_O(BAT-REG)
– 0.075
V_O(BAT-REG)
– 0.100
V_O(BAT-REG)
– 0.125
T_DGL(RCH)
Deglitch time for recharge R_(TMR) = 50 kΩ, V_I(BAT) increasing or decreasing below
detection ⁽¹⁴⁾
threshold, 100-ns fall time, 10-mV overdrive
STAT1, STAT2. ACPG, USBPG Open-Drain (OD) Outputs⁽¹⁵⁾
22.5
V_OL
Low-level output saturation
voltage
I_OL = 5 mA, External pullup resistor ≥ 1 kΩ required
0.25
I_LKG
Input leakage current
ISET2, CE Inputs
1
5
V_IL
Low-level input voltage
V_IH
High-level input voltage
I_IL
Low-level input current, CE
I_IH
High-level input current,
CE
0
0.4
1.4
–1
1
I_IL
Low-level input current,
ISET2
V_ISET2 = 0 V
–20
I_IH
High-level input current,
ISET2
V_ISET2 = V_CC
40
I_IL1
I_IH1
t_(CE-HLDOFF)
PSEL Input
Low-level input current
High-level input current
Holdoff time, CE
CE going low only
6
1
15
3.3
6.2
V_IL
Low-level input voltage
Falling high→low, 280 kΩ ± 10% applied when low
0.975
1
1.025
V_IH
High-level input voltage
Input R_PSEL sets external hysteresis
V_IL + 0.01
V_IL + 0.024
I_IL
Low-level input current,
PSEL
–1
I_IH
High-level input current,
PSEL
UNIT
mA
mV
mV
ms
V
V
μA
ms
V
ms
V
μA
V
μA
μA
μA
μA
μA
μA
ms
V
V
μA
μA
(14) All deglitch periods are a function of the timer setting and is modified in DPPM or thermal regulation modes by the percentages that the
program current is reduced.
(15) See Charger Sleep mode for ACPG (V_CC = V_AC) and USBPG (V_CC = V_USB) specifications.
6
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