DM3730_17 Datasheet, PDF (55/280 Pages) Texas Instruments – Digital Media Processors

DM3730, DM3725
www.ti.com
SPRS685D – AUGUST 2010 – REVISED JULY 2011
BALL
BOTTOM
[1]
E3
E4
G3
D4
AE14
W11
W15
V16
V13
AD7
V12
AF19
AF20
W26
V26
W25
U24
V23
AE20
A24
B24
Table 2-2. Ball Characteristics (CBC Pkg.)⁽⁵⁾ (continued)
BALL TOP PIN NAME [2]
[1]
safe_mode
NA
sys_boot3
dss_data20
gpio_5
safe_mode
NA
sys_boot4
mmc2_dir_dat2
dss_data21
gpio_6
safe_mode
NA
sys_boot5
mmc2_dir_dat3
dss_data22
gpio_7
safe_mode
NA
sys_boot6
dss_data23
gpio_8
safe_mode
NA
sys_clkout1
gpio_10
safe_mode
NA
sys_clkout2
gpio_186
safe_mode
NA
sys_clkreq
gpio_1
safe_mode
NA
sys_nirq
gpio_0
safe_mode
NA
sys_nrespwron
AA5
sys_nreswarm
gpio_30
safe_mode
NA
sys_off_mode
gpio_9
safe_mode
NA
sys_xtalin
NA
sys_xtalout
NA
cvideo1_out
NA
cvideo2_out
NA
cvideo1_vfb
NA
cvideo2_vfb
NA
cvideo1_rset
NA
sys_32k
NA
cam_d2
gpio_101
hw_dbg4
safe_mode
NA
cam_d3
gpio_102
hw_dbg5
safe_mode
MODE [3] TYPE [4]
7
-
0
I
3
O
4
IO
7
-
0
I
1
O
3
O
4
IO
7
-
0
I
1
O
3
O
4
IO
7
-
0
I
3
O
4
IO
7
-
0
O
4
IO
7
-
0
O
4
IO
7
-
0
IO
4
IO
7
-
0
I
4
IO
7
-
0
I
0
IOD
4
IO
7
-
0
O
4
IO
7
-
0
AI
BALL
BALL RESET RESET
POWER [8] HYS [9]
RESET
REL. STATE REL. MODE
STATE [5] [6]
[7]
Z
Z
0
vdds
Yes
Z
Z
0
vdds
Yes
Z
Z
0
vdds
Yes
Z
Z
0
vdds
Yes
L
L
7⁽¹²⁾
vdds
Yes
L
L
7
vdds
Yes
0
see ⁽⁷⁾
0
vdds
Yes
H
H
7
vdds
Yes
Z
Z
0
H
0
vdds
Yes
0
vdds
Yes
0
L
7
vdds
Yes
Z
Z
0
vdds
Yes
0
AO
Z
0
0
vdds
NA
0
AO
0
0
0
vdda_dac NA
0
AO
0
0
0
vdda_dac NA
0
AO
0
NA
0
vdda_dac NA
0
AO
0
NA
0
vdda_dac NA
0
AIO
Z
NA
0
vdda_dac No
0
I
Z
Z
0
vdds
Yes
0
I
L
L
7
vdds
Yes
4
IO
5
O
7
-
0
I
L
L
7
vdds
Yes
4
IO
5
O
7
-
BUFFER PULLUP
STRENGTH /DOWN
(mA) [10] TYPE [11]
IO CELL
[12]
8
PU/ PD
LVCMOS
8
PU/ PD
LVCMOS
8
PU/ PD
LVCMOS
8
PU/ PD
LVCMOS
4
PU/ PD
LVCMOS
4
PU/ PD
LVCMOS
4
PU/ PD
LVCMOS
4
PU/ PD
LVCMOS
NA
No
LVCMOS
4
PU/ PD
LVCMOS
Open Drain
4
PU/ PD
LVCMOS
NA
NA
LVCMOS
Analog
NA
NA
Analog
NA
NA
10-bit DAC
NA
NA
10-bit DAC
NA
NA
10-bit DAC
NA
NA
10-bit DAC
NA
NA
10-bit DAC
NA
PU/ PD
LVCMOS
8
PU/ PD
LVCMOS
8
PU/ PD
LVCMOS
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