DM3730_17 Datasheet, PDF (143/280 Pages) Texas Instruments – Digital Media Processors

DM3730, DM3725
www.ti.com
SPRS685D – AUGUST 2010 – REVISED JULY 2011
4.3.3 DPLL and DLL Noise Isolation
The noise filters (decoupling capacitors) are required to suppress the switching noise generated by high
frequency and to stabilize the supply voltage.
A noise filter is most effective when it is close to the device, because this minimizes the inductance of the
circuit board wiring and interconnects.
Figure 4-8 illustrates an example of a noise filter.
DPLL_MPU
DPLL_IVA
DPLL_CORE
DLL
DPLL5
DPLL4
Noise Filter
vdda_dplls_dll
C
Noise Filter
vdda_dpll_per
C
A. This circuit is provided only as an example.
B. The filter must be located as close as possible to the device.
Figure 4-8. DPLL Noise Filter
030-017
Table 4-17 specifies the noise filter requirements.
Table 4-17. DPLL Noise Filter Requirements(1)
NAME
MIN
TYP
Filtering capacitor
50
100
(1) For more information, see IO and Analog Voltage Decoupling Capacitors.
MAX
150
UNIT
nF
4.3.4 Processor Clocks
Table 4-18 through Table 4-20 show the clocks AC performance values.
Table 4-18. Processor Voltages Without SmartReflex^TM
RETENTIO
N
OPP50
OPP100
MIN
MIN
TYP
MAX
MIN
TYP
MAX
MIN
VDD1^{(1) (2)}
0.8
0.92
0.97
1.02
1.08
1.14
1.2
1.21
(V)
(1) At ball level.
(2) Minimum OPP voltage values defined in this table include any voltage transient.
(3) OPP130 is not available above T_J of 90C.
Table 4-19. Processor Voltages With SmartReflex^TM
RETENTIO
N
MIN
MIN
OPP50
TYP
MAX
OPP100
MIN
TYP
MAX
OPP130⁽⁴⁾
MIN
TYP
MAX
OPP130⁽³⁾
TYP
1.27
MAX
1.33
OPP1G ^{(4) (5)(6)}
MIN
TYP
MAX
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Clock Specifications 143