DM3730_17 Datasheet, PDF (197/280 Pages) Texas Instruments – Digital Media Processors

DM3730, DM3725
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cam_xclki
ISP16
ISP15
ISP16
SPRS685D – AUGUST 2010 – REVISED JULY 2011
cam_pclk
ISP3
ISP4
ISP4
cam_vs
ISP5
ISP6
cam_hs
ISP7
ISP8
cam_d[7:0]
ISP9
D(0)
D(n-3) D(n-2)
D(n-1)
ISP10
D(0)
D(1)
D(n-1)
cam_wen
cam_fld
ISP11
ISP12
SWPS038-051
(1) The polarity of cam_pclk, cam_fld, cam_vs, and cam_hs are configurable.
(2) The image sensor is connected to the lower data lines and the unused lines are grounded. However, it is possible to shift the data to
0, 2, or 4 data internal lanes. The bit configurations are: cam_d[11:4] or cam_d[7:0] in 8-bit packed mode.
(3) Optionally, the data write to memory can be qualified by the external cam_wen signal. The cam_wen signal can be used as a
external memory write-enable signal. The data is stored to memory only if cam_hs, cam_vs, and cam_wen signals are asserted. The
polarity of cam_fld is programmable.
(4) The camera module can pack 8-bit data into 16 bits. It doubles the maximum pixel clock. This mode can be particularly useful to
transfer an YCbCr data stream or compressed stream to memory at very high speed.
(5) In cam_xclki, i can be equal to a or b. See Table 6-22 for ISP15 and ISP16 parameters.
Figure 6-26. CPI—8-Bit SYNC Packed Progressive Mode
6.5.1.2.4 CPI—12-Bit SYNC Normal Interlaced Mode
Table 6-30 assumes testing over the recommended operating conditions and electrical characteristic
conditions below (see Figure 6-27).
Table 6-29. CPI Timing Conditions—12-Bit SYNC Normal Interlaced Mode
TIMING CONDITION PARAMETER
Input Conditions
t_R
Input signal rise time
t_F
Input signal fall time
Output Condition
C_LOAD
Output load capacitance⁽¹⁾
(1) The load setting of the IO buffer: LB0 = 1.
VALUE
2.7
2.7
8.6
UNIT
ns
ns
pF
Copyright © 2010–2011, Texas Instruments Incorporated
Timing Requirements and Switching Characteristics 197
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