DM3730_17 Datasheet, PDF (200/280 Pages) Texas Instruments – Digital Media Processors

DM3730, DM3725
SPRS685D – AUGUST 2010 – REVISED JULY 2011
www.ti.com
6.5.1.2.5 CPI—8-Bit SYNC Packed Interlaced Mode
Table 6-32 assumes testing over the recommended operating conditions and electrical characteristic
conditions below (see Figure 6-28).
Table 6-31. CPI Timing Conditions—8-Bit SYNC Packed Interlaced Mode
TIMING CONDITION PARAMETER
Input Conditions
t_R
Input signal rise time
t_F
Input signal fall time
Output Condition
C_LOAD
Output load capacitance⁽¹⁾
(1) The load setting of the IO buffer: LB0 = 1.
VALUE
2.5
2.5
8.6
UNIT
ns
ns
pF
Table 6-32. CPI Timing Requirements—8-Bit SYNC Packed Interlaced Mode^{(4) (5)}
NO.
ISP3
ISP4
ISP4
1 / t_c(pclk)
t_w(pclkH)
t_w(pclkL)
t_dc(pclk)
t_J(pclk)
PARAMETER
Frequency⁽¹⁾, input pixel clock cam_pclk
Typical pulse duration, input pixel clock cam_pclk high
Typical pulse duration, input pixel clock cam_pclk low
Duty cycle error, input pixel clock cam_pclk
Cycle jitter⁽³⁾, input pixel clock cam_pclk
OPP100
MIN
MAX
130
0.5P⁽²⁾
0.5P⁽²⁾
0.5*P⁽²⁾ -
3.465
0.0649*P
(2)
ISP5 t_su(dV-pclkH)
Setup time, input data cam_d[8:0] valid before input
pixel clock cam_pclk rising edge
1.08
ISP6 t_h(pclkH-dV)
Hold time, input data cam_d[8:0] valid after input pixel 1.08
clock cam_pclk rising edge
ISP7 t_su(dV-vsH)
Setup time, input vertical synchronization cam_vs valid 1.08
before input pixel clock cam_pclk rising edge
ISP8 t_h(pclkH-vsV)
Hold time, input vertical synchronization cam_vs valid 1.08
after input pixel clock cam_pclk rising edge
ISP9 t_su(dV-hsH)
Setup time, input horizontal synchronization cam_hs
1.08
valid before input pixel clock cam_pclk rising edge
ISP10 t_h(pclkH-hsV)
Hold time, input horizontal synchronization cam_hs
valid after input pixel clock cam_pclk rising edge
1.08
ISP11 t_su(dV-hsH)
Setup time, input write enable cam_wen valid before
1.08
input pixel clock cam_pclk rising edge
ISP12 t_h(pclkH-hsV)
Hold time, input write enable cam_wen valid after input 1.08
pixel clock cam_pclk rising edge
ISP13 t_su(dV-fldH)
Setup time, input field identification cam_fld valid
before input pixel clock cam_pclk rising edge
1.08
ISP14 t_{h(pclkH-fldV)}
Hold time, input field identification cam_fld valid after
input pixel clock cam_pclk rising edge
1.08
(1) Related with the input maximum frequency supported by the ISP module.
(2) P = cam_pclk period in ns
(3) Maximum cycle jitter supported by cam_pclk input clock.
(4) The timing requirements are assured up to the cycle jitter and duty cycle error conditions specified.
(5) See Section 4.3.4, Processor Clocks.
OPP50
MIN
MAX
65
0.5P⁽²⁾
0.5P⁽²⁾
0.5*P⁽²⁾ -
6.93
0.0649*P
(2)
2.27
2.27
2.27
2.27
2.27
2.27
2.27
2.27
2.27
2.27
UNIT
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
200 Timing Requirements and Switching Characteristics
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