66AK2G02_16 Datasheet, PDF (51/230 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

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66AK2G02, 66AK2G01
SPRS932C – DECEMBER 2015 – REVISED NOVEMBER 2016
Table 4-8. SPI Signal Descriptions (continued)
SIGNAL NAME [1]
DESCRIPTION [2]
PIN
TYPE [3]
ZBB BALL [4]
SPI3_SOMI
SPI Data Input
IOZ
F25
(1) This clock signal is implemented as pad loopback inside the device — the output signal is looped back through the input buffer to serve
as the internal reference signal. Series termination is recommended (as close as possible to device pin) to improve signal integrity of the
clock input.
For more information, see section Serial Peripheral Interface (SPI) in chapter Peripherals of the device
TRM.
4.3.8 QSPI
SIGNAL NAME [1]
QSPI_CLK
QSPI_CSn0
QSPI_CSn1
QSPI_CSn2
QSPI_CSn3
QSPI_D0
QSPI_D1
QSPI_D2
QSPI_D3
QSPI_RCLK
Table 4-9. QSPI Signal Descriptions
DESCRIPTION [2]
QSPI Serial Clock Output
QSPI Chip Select 0 (Active Low). This pin is used for
QSPI boot modes.
QSPI Chip Select 1 (Active Low)
QSPI Chip Select 2 (Active Low)
QSPI Chip Select 3 (Active Low)
QSPI Data 0. This pin is output data for all commands
and writes. For dual read and quad read modes, it
becomes input data pin during read phase.
QSPI Data 1. Input read data in all modes.
QSPI Data 2. This pin is used only in quad read mode as
input data pin during read phase.
QSPI Data 3. This pin is used only in quad read mode as
input data pin during read phase.
QSPI Return Clock Input. Must be connected from
QSPI_SCLK on PCB. Refer to PCB Guidelines for QSPI.
PIN
TYPE [3]
OZ
OZ
OZ
OZ
OZ
IOZ
IOZ
IOZ
IOZ
I
ZBB BALL [4]
K25
J25
H23
H22
H21
J23
J22
J21
J24
K24
For more information, see section Quad Serial Peripheral Interface (QSPI) in chapter Peripherals of the
device TRM.
4.3.9 McASP
SIGNAL NAME [1]
MCASP0_ACLKR⁽¹⁾
MCASP0_ACLKX⁽¹⁾
MCASP0_AFSR
MCASP0_AFSX
MCASP0_AHCLKR
MCASP0_AHCLKX
MCASP0_AMUTE
MCASP0_AXR0
MCASP0_AXR1
MCASP0_AXR2
MCASP0_AXR3
MCASP0_AXR4
MCASP0_AXR5
Table 4-10. McASP Signal Descriptions
DESCRIPTION [2]
McASP0 Receive Bit Clock I/O
McASP0 Transmit Bit Clock I/O
McASP0 Receive Frame Sync I/O
McASP0 Transmit Frame Sync I/O
McASP0 Receive High-Frequency Master Clock I/O
McASP0 Transmit High-Frequency Master Clock Output
McASP0 Mute
McASP0 Transmit and Receive Data I/O
McASP0 Transmit and Receive Data I/O
McASP0 Transmit and Receive Data I/O
McASP0 Transmit and Receive Data I/O
McASP0 Transmit and Receive Data I/O
McASP0 Transmit and Receive Data I/O
PIN
TYPE [3]
IOZ
IOZ
IOZ
IOZ
IOZ
OZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
ZBB BALL [4]
E9
D9
A8
C8
B8
C9
C7
B9
A9
B10
A10
C10
E10
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Terminal Configuration and Functions
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