66AK2G02_16 Datasheet, PDF (138/230 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

66AK2G02, 66AK2G01
SPRS932C – DECEMBER 2015 – REVISED NOVEMBER 2016
www.ti.com
5.9.4.7 McASP
For more details about features and additional description information on the device Multichannel Audio
Serial Port, see the corresponding sections within Section 4.3, Signal Descriptions and Section 6, Detailed
Description.
Table 5-50, Table 5-51, and Figure 5-40 present timing requirements for McASP0 to McASP2.
Table 5-50. Timing Requirements for McASP⁽⁴⁾
NO.
ASP1
ASP2
ASP3
ASP4
t_c(AHCLKRX)
t_w(AHCLKRX)
t_c(ACLKRX)
t_w(ACLKRX)
ASP5 t_{su(AFSRX-ACLKRX)}
Cycle time, McASP[x]_AHCLKR/X
Pulse duration, McASP[x]_AHCLKR/X high or low
Cycle time, McASP[x]_ACLKR/X
Pulse duration, McASP[x]_ACLKR/X high or low
Setup time, McASP[x]_AFSR/X input valid
before McASP[x]_ACLKR/X
ACLKR/X int
ACLKR/X ext in
ACLKR/X ext out
ASP6 t_{h(ACLKRX-AFSRX)}
Hold time, McASP[x]_AFSR/X input valid after
McASP[x]_ACLKR/X
ACLKR/X int
ACLKR/X ext in
ACLKR/X ext out
ASP7 t_{su(AXR-ACLKRX)}
Setup time, McASP[x]_AXR input valid before
McASP[x]_ACLKR/X
ACLKR/X int
ACLKR/X ext in
ACLKR/X ext out
ASP8 t_{h(ACLKRX-AXR)}
Hold time, McASP[x]_AXR input valid after
McASP[x]_ACLKR/X
ACLKR/X int
ACLKR/X ext in
ACLKR/X ext out
(1) ACLKR internal: ACLKRCTL.CLKRM = 1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR external output: ACLKRCTL.CLKRM = 0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX external output: ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
(2) P = McASP[x]_AHCLKR and McASP[x]_AHCLKX period in ns.
(3) R = McASP[x]_ACLKR and McASP[x]_ACLKX period in ns.
(4) x in McASP[x]_* is 0, 1 or 2
MIN
20
0.5P - 2.5⁽²⁾
20
0.5R - 2.5⁽³⁾
12.3
4
4
-1
1.6
1.6
12.3
4
4
-1
1.6
1.6
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
138 Specifications
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