66AK2G02_16 Datasheet, PDF (175/230 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

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66AK2G02, 66AK2G01
SPRS932C – DECEMBER 2015 – REVISED NOVEMBER 2016
Fore more information about:
• C66x CorePac, see the TMS320C66x DSP CorePac User's Guide (SPRUGW0).
• C66x CPU core, see the TMS320C66x DSP CPU and Instruction Set Reference Guide (SPRUGH7).
• C66x cache memory system, see the TMS320C66x DSP Cache User's Guide (SPRUGY8).
• C66x debug/trace support, see chapter On-chip Debug of the device TRM.
6.5 C66x Cache Subsystem
The purpose of this section is to provide an overview of the C66x cache memory architecture and to
specify its configuration in this device. Details on the C66x cache functionality can be found in the
TMS320C66x DSP Cache User Guide (SPRUGY8).
The device contains a 1024KB level-2 memory (L2), a 32KB level-1 program memory (L1P), and a 32KB
level-1 data memory (L1D). Each memory has a unique location in the memory map (see chapter Memory
Map of the device TRM).
After device reset, L1P and L1D cache are configured as all cache, by default. The L1P and L1D cache
can be reconfigured via software through the L1PMODE field of the L1P Configuration Register
(L1PMODE) and the L1DMODE field of the L1D Configuration Register (L1DCFG) of the C66x CorePac.
L1D is a two-way set-associative cache, while L1P is a direct-mapped cache.
For more information, see section C66x Cache Subsystem in chapter Processors and Accelerators of
the device TRM.
6.6 PRU-ICSS
The Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
consists of:
• Two 32-bit load/store RISC CPU cores — Programmable Real-Time Units (PRU0 and PRU1)
• Data RAMs per PRU core
• Instruction RAMs per PRU core
• Shared RAM
• Peripheral modules
• Interrupt controller (ICSS_INTC).
The programmable nature of the PRU cores, along with their access to pins, events and all device
resources, provides flexibility in implementing fast real-time responses, specialized data handling
operations, custom peripheral interfaces, and in offloading tasks from the other processor cores of the
device.
The device has integrated two identical PRU subsystems (PRU-ICSS_0 and PRU-ICSS_1).
The PRU cores within each PRU-ICSS have access to all resources on the SoC through the Interface
Master port, and the external host processors can access the PRU-ICSS resources through the Interface
Slave port. The 32-bit interconnect bus connects the various internal and external masters to the
resources inside the PRU-ICSS. The PRU cores within the subsystems also have access to all resources
on the SoC through the TeraNet DMA Interconnect. A subsystem local Interrupt Controller — ICSS_INTC
handles system input events and posts events back to the device-level host CPUs.
The PRU cores are programmed with a small, deterministic instruction set. Each PRU can operate
independently or in coordination with each other and can also work in coordination with the device-level
host CPU. This interaction between processors is determined by the nature of the firmware loaded into the
PRU’s instruction memory.
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Detailed Description 175