66AK2G02_16 Datasheet, PDF (199/230 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

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66AK2G02, 66AK2G01
SPRS932C – DECEMBER 2015 – REVISED NOVEMBER 2016
For more information, see section Universal Asynchronous Receiver/Transmitter (UART) in chapter
Peripherals of the device TRM.
6.10.18 USB
Similar to earlier versions of USB bus, USB 2.0 is a general-purpose cable bus, supporting data exchange
between a host device and a wide range of simultaneously accessible peripherals.
The device supports two USB 2.0 subsystems with High Speed Dual-Role-Device (DRD) ports with
integrated PHY.
The USB 2.0 subsystem, supports the following USB features:
• Dual-role-device (DRD) capability:
– Supports USB 2.0 Peripheral (or Device) mode at Highspeed (480 Mbps) and Fullspeed (12 Mbps)
– Supports USB 2.0 Host mode at Highspeed (480 Mbps), Fullspeed (12 Mbps), and Lowspeed (1.5
Mbps)
– USB 2.0 static peripheral operation
– USB 2.0 static host operation
– xHCI Debug Capability
– External Buffer Control (EBC) mode for IN (Tx) Endpoint
• Each controller instance contains single xHCI with the following features:
– Compatible to the xHCI Specification (Revision 1.1) in Host mode
– Supports 15 Transmit (TX), 15 Receive (RX) endpoints (EPs), and one EP0 endpoint which is
bidirectional
– Internal DMA controller
– Interrupt moderation and blocking
– Supports for all USB transfer modes - Control, Bulk, Interrupt, and Isochronous
– Supports high bandwidth ISO mode
– Descriptor caching and data pre-fetching used to improve system performance
– Dynamic FIFO memory allocation for all endpoints
• Operation flexibility:
– Uniform programming model for HS, FS, and LS operation
– Multiple interrupt lines:
• 16 interrupts associated with 16 programmable Event Rings for multi-core support
• A MISC interrupt line for all miscellaneous events
• ECC RAM
• External requirements:
– An external charge pump for VBUS 5 V generation
– An external reference clock input for USB PHY operation
– An external high-precision resistor for internal PHY termination calibration
The following are USB features which are not supported:
• USB 3.0 SuperSpeed (5 Gbps) or USB3.1 SuperSpeed+ (10 Gbps) operation in either host or device
modes
• OTG Functionality
• HSIC (High Speed inter-chip)
• ULPI Interface for external PHY
• Battery Charger Support
• Accessory Charger Adaptor Support
• xHCI Virtualization
• Hibernation (separate power domain for wake up from USB and save/ restore on wakeup) mode
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Detailed Description 199