66AK2G02_16 Datasheet, PDF (108/230 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

66AK2G02, 66AK2G01
SPRS932C – DECEMBER 2015 – REVISED NOVEMBER 2016
www.ti.com
Table 5-23. DPI Video Output Switching Characteristics (continued)
NO.
PARAMETER
D6
t_d(clk-dV)
Delay time, output pixel clock DSS_PCLK transition to output control
signals DSS_VSYNC, DSS_HSYNC, DSS_DE, and DSS_FID valid
(1) P = output DSS_PCLK period in ns.
MIN
-1.39
MAX UNIT
1.15 ns
D2
D1
D3
D4
DSS_PCLK
DSS_PCLK
D6
DSS_VSYNC
Falling-edge Clock Reference
Rising-edge Clock Reference
D6
DSS_HSYNC
DSS_DATA[23:0]
DSS_DE
D5
data_1 data_2
D6
data_n
D6
DSS_FID
odd
even
SWPS049-018
(1) The configuration of assertion of the data can be programmed on the falling or rising edge of the pixel clock.
(2) The polarity and the pulse width of DSS_HSYNC and DSS_VSYNC are programmable, refer to section Display Subsystem (DSS) in
chapter Peripherals of the device TRM.
(3) The DSS_PCLK frequency can be configured, refer to section Display Subsystem in chapter Peripherals of the device TRM.
Figure 5-11. DPI Video Output ^(1)(2)(3)
5.9.4.3 EMIF
For more details about features and additional description information on the device DDR3L Memory
Interface, see the corresponding sections within Section 4.3, Signal Descriptions and Section 6, Detailed
Description.
The device has a dedicated interface to DDR3L SDRAM. It supports JEDEC JESD79-3F and JESD79-3-1
standards compliant DDR3L SDRAM devices with the following features:
• 16-bit or 32-bit data path to external SDRAM memory
• Memory device capacity: Up to 4 GB address space available over one chip select
5.9.4.4 EMAC
For more details about features and additional description information on the device Gigabit Ethernet
MAC, see the corresponding sections within Section 4.3, Signal Descriptions and Section 6, Detailed
Description.
108 Specifications
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