66AK2G02_16 Datasheet, PDF (195/230 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

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66AK2G02, 66AK2G01
SPRS932C – DECEMBER 2015 – REVISED NOVEMBER 2016
6.10.13 PCIESS
Peripheral Component Interconnect Express (PCIE) controllers provide a high-speed glueless serial
interconnect to peripherals utilizing high bandwidth applications.
PCIe module is a multi-lane I/O interconnect that provides low pin-count, high reliability, and high-speed
data transfer at rates of up to 5.0 Gbps per lane, per direction, for serial links on backplanes and printed
curcuit boards. It is a 2nd generation I/O interconnect technology succeeding PCI and ISA bus designed
to be used as a general-purpose serial I/O interconnect. It is also used as a bridge to other interconnects
such as SATA, USB2/3.0, GbE MAC, and so forth.
The PCI Express standard's predecessor - PCI, is a parallel bus architecture that is increasingly difficult to
scale-up in bandwidth, which is usually performed by increasing the number of data signal lines. The PCIe
architecture was developed to help minimize I/O bus bottlenecks within systems and to provide the
necessary bandwidth for high-speed, chip-to-chip, and board-to-board communications within a system. It
is designed to replace the PCI-based shared, parallel bus signaling technology that is approaching its
practical performance limits while simplifying the interface design.
PCIe module supports the following features:
• Dual operation mode: Root Complex (RC) or End Point (EP)
• Supports a single bidirectional link interface (a single input port and a single output port) with one lane
• Operated at a raw speed of 2.5 Gbps or 5.0 Gbps per lane per direction
• Maximum outbound payload size of 128 bytes
• Maximum inbound payload size of 256 bytes
• Maximum remote read request size of 256 bytes
• Ultra-low transmit and receive latency
• Support for dynamic-width conversion
• Automatic lane reversal
• Polarity inversion on receive
• Single virtual channel (VC)
• Single traffic class (TC)
• Single function in End Point (EP) mode
• Automatic credit management
• ECRC generation and checking
• PCI device power management with the exception of D3cold with Vaux
• PCI Express active state power management (ASPM) state L0s and L1
• PCI Express link power management states, except L2 state
• PCI Express advanced error reporting
• PCI Express messages for both transmit and receive
• Filtering for posted, non-posted, and completion traffic
• Configurable BAR filtering, I/O filtering, configuration filtering, and completion lookup/timeout
• Access to configuration space registers and external application memory-mapped registers through
BAR0 and through configuration access
• Legacy interrupts reception (in RC) and generation (in EP)
• MSI generation and reception
• PHY loopback in RC mode
PCIe module does not support the following features:
• No support for multiple lanes
• No support for multiple VCs
• No support for multiple TCs
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Detailed Description 195