SMJ320C25GBM Datasheet, PDF (5/38 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C25, SMJ320C25Ć50
DIGITAL SIGNAL PROCESSOR
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
architecture
The SMJ320C25 increases performance of DSP algorithms through innovative additions to the SMJ320
architecture. Increased throughput on the SMJ320C25 for many DSP applications is accomplished by means
of single-cycle multiply/accumulate instructions with a data move option, eight auxiliary registers with a
dedicated arithmetic unit, and faster I/O necessary for data-intensive signal processing.
The architectural design of the SMJ320C25 emphasizes overall speed, communication, and flexibility in
processor configuration. Control signals and instructions provide floating-point support, block-memory
transfers, communication to slower off-chip devices, and multiprocessing implementations.
Two large on-chip RAM blocks, configurable either as separate program and data spaces or as two contiguous
data blocks, provide increased flexibility in system design. Programs of up to 4K words can be masked into the
internal program ROM. The remainder of the 64K-word program memory space is located externally. Large
programs can execute at full speed from this memory space. Programs can also be downloaded from slow
external memory to high-speed on-chip RAM. A total of 64K data memory address space is included to facilitate
implementation of DSP algorithms. The VLSI implementation of the SMJ320C25 incorporates all of these
features as well as many others, such as a hardware timer, serial port, and block data transfer capabilities.
32-bit ALU/accumulator
The SMJ320C25 32-bit arithmetic logic unit (ALU) and accumulator perform a wide range of arithmetic and
logical instructions, the majority of which execute in a single clock cycle. The ALU executes a variety of branch
instructions dependent on the status of the ALU or a single bit in a word. These instruction provide the following
capabilities:
D Branch to an address specified by the accumulator
D Normalize fixed-point numbers contained in the accumulator
D Test a specified bit of a word in data memory.
One input to the ALU is always provided from the accumulator, and the other input can be provided from the
product register (PA) of the multiplier or the input scaling shifter which has fetched data from the RAM on the
data bus. After the ALU has performed the arithmetic or logical operations, the result is stored in the
accumulator.
The 32-bit accumulator is split into two 16-bit segments for storage in data memory. Additional shifters at the
output of the accumulator perform shifts while the data is being transferred to the data bus for storage. The
contents of the accumulator remain unchanged.
scaling shifter
The SMJ320C25 scaling shifter has a 16-bit input connected to the data bus and a 32-bit output connected to
the ALU. The scaling shifter produces a left shift of 0 to 16 bits on the input data, as programmed in the
instruction. The LSBs of the output are filled with zeroes, and the MSBs can be either filled with zeroes or
sign-extended, depending upon the status programmed into the SXM (sign-extension mode) bit of status
register ST1.
16 X 16-bit parallel multiplier
The SMJ320C25 has a 16 x 16-bit hardware multiplier, which is capable of computing a signed or unsigned
32-bit product in a single machine cycle. The multiplier has the following two associated registers:
D A 16-bit temporary register (TR) that holds one of the operands for the multiplier, and
D A 32-bit product register (PR) that holds the product.
Incorporated into the SMJ320C25 instruction set are single-cycle multiply/accumulate instruction that allow
both operands to be processed simultaneously. The data for these operations can reside anywhere in internal
or external memory and can be transferred to the multiplier each cycle via the program and data buses.
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