SMJ320C25GBM Datasheet, PDF (19/38 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C25, SMJ320C25Ć50
DIGITAL SIGNAL PROCESSOR
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
external clock option
An external frequency source can be used by injecting the frequency directly into X2/CLKIN with X1 left
unconnected. The external frequency injected must conform to the specifications listed in the following table.
switching characteristics over recommended operating conditions (see Note 1)
PARAMETER
tc(C)
td(CIH_–C)
td(C1_–C2)
Cycle time, CLKOUT1/CLKOUT2
Delay time, CLKIN high to CLKOUT1/CLKOUT2/STRB high/low
Delay time, CLKOUT1 high to CLKOUT2 low,
Delay time, CLKOUT2 high to CLKOUT1 high, etc.
tf(C)
Fall time, CLKOUT1/CLKOUT2/STRB
tr(C)
Rise time, CLKOUT1/CLKOUT2/STRB
tw(CL)
Pulse duration, CLKOUT1/CLKOUT2 low
tw(CH)
Pulse duration, CLKOUT1/CLKOUT2 high
† _{.This parameter is not production tested}
NOTE 1: Q = 1/4tc(C)
SMJ320C25-50
MIN MAX
80
600
5
28
SMJ320C25
MIN NOM MAX
100
600
5
30
Q–6 Q+3 Q–6
2Q – 7
2Q – 5
5
3
2Q + 5
2Q + 7
2Q – 8
2Q – 8
Q Q+6
5
5
2Q 2Q + 8
2Q 2Q + 8
UNIT
ns
(1S
ns
ns
ns
ns
ns
timing requirements over recommended operating conditions (see Note 1 )
SMJ320C25-50
MIN MAX
SMJ320C25
MIN MAX
UNIT
tc(CI)
Cycle time, CLKIN
20 150
25 150 ns
tw(CIL)
Pulse duration, CLKIN low, tc(CI) = 25 ns (see Note 2)
8
10
15 ns
tw(CIH)
Pulse duration, CLKIN high, tc(CI) = 25 ns (see Note 2)
8
10
15 ns
tsu(S)
Setup time, SYNC before CLKIN low
4 Q–4
5 Q – 5 ns
th(S)
Hold time, SYNC from CLKIN low
4
8
ns
NOTES: 1: Q = 1/4tc(C)
2. Rise and fall times, assuming a 40–60% duty cycle, are incorporated within this specification CLKIN rise and fall times must be less
than 5 ns
Figure 3. Test Load Circuit
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