SMJ320C25GBM Datasheet, PDF (30/38 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C25, SMJ320C25Ć50
DIGITAL SIGNAL PROCESSOR
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
CLKOUT1
CLKOUT2
STRB
HOLD
td(C2H-H)^†
A15-A0
N
N+1
N+2
PS, DS,
or IS
Valid
Valid
R/W
D15-D0
In
In
HOLDA
tdis(C1L-A)
tdis(AL-A)
td(C1L-AL)
N
N+1
–
–
FETCH
N–2
N –1
N
–
EXECUTE
† _{HOLD is an asynchronous input and can occur at any time during a clock cycle. If the specified timing is met, the exact sequence shown occurs;}
otherwise, a delay of one CLKOUT2 cycle occurs.
Figure 13. HOLD Timing (part A)
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