SMJ320C25GBM Datasheet, PDF (31/38 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

CLKOUT1
SMJ320C25, SMJ320C25Ć50
DIGITAL SIGNAL PROCESSOR
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
CLKOUT2
STRB
HOLD
td(C2H-H)^†
ten(A-C1L)
PS, DS,
or IS
R/W
Valid
D15-D0
In
HOLDA
td(HH-AH)
A15-A0
N+2
N+2
–
–
–
N+2
FETCH
–
–
–
N+1
EXECUTE
† _{HOLD is an asynchronous input and can occur at any time during a clock cycle. If the specified timing is met, the exact sequence shown occurs;}
otherwise, a delay of one CLKOUT2 cycle occurs.
Figure 14. HOLD Timing (part B)
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
31