SMJ320C25GBM Datasheet, PDF (21/38 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

RS, INT, BIO, and XF timing
SMJ320C25, SMJ320C25Ć50
DIGITAL SIGNAL PROCESSOR
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
switching characteristics over recommended operating conditions (see Note 1)
PARAMETER
td(RS)
td(IACK)
td(XF)
Delay time, CLKOUT1 low to reset state entered
Delay time, CLKOUT1 to IACK valid
Delay time, XF valid before falling edge of STRB
SMJ320C25-50
SMJ320C25
MIN TYP MAX
22^†
–5^†
0
7
MIN TYP MAX
22^†
–8^†
0
8
Q – 10
Q – 12
UNIT
ns
ns
ns
timing requirements over recommended operating conditions (see Note 1)
tsu(IN)
th(IN)
tw(IN)
tw(RS)
Setup time, INT/BIO/RS before CLKOUT1 high
Hold time, INT/BIO/RS after CLKOUT1 high
Pulse duration, INT/BIO low
Pulse duration, RS low
SMJ320C25-50
MIN MAX
25
0
tc(C)
3tc(C)
SMJ320C25
MIN MAX
32
0
tc(C)
3tc(C)
UNIT
ns
ns
ns
ns
switching characteristics over recommended operating conditions (see Note 1)
PARAMETER
td(C1L-AL)
tdis(AL-A)
tdis(C1L-A)
Delay time, HOLDA low after CLKOUT1 low
Disable time, HOLDA low to address three-state
Disable time, address three-state after CLKOUT1 low (HOLD
mode, see Note 7 )
td(HH-AH) Delay time, HOLD high to HOLDA high
ten(A-C1L)
Enable time, address driven before CLKOUT1 low (HOLD mode,
see Note 7 )
SMJ320C25-50
MIN TYP MAX
–1
11
0
20^†
19
8^†
SMJ320C25
MIN TYP MAX
–1
10
0
20^†
25
8^†
UNIT
ns
ns
ns
ns
ns
timing requirements over recommended operating conditions (see Note 1)
SMJ320C25-50 SMJ320C25
UNIT
MIN MAX MIN MAX UNIT
td(C2H-H) Delay time, HOLD valid after CLKOUT2 high
Q – 19
Q – 24 ns
† _{These values are derived from characterization data and not tested.}
NOTES: 1. Q = 1/4tc(C)
6. RS, INT, and BIO are asynchronous inputs and can occur at any time during a clock cycle. However, if the specified setup time is
met, the exact sequence shown in the timing diagram occurs. INT/BIO fall time must be less than 8 ns.
7. A15–A0, PS, DS, IS, STRB, and R/W timings are all included in timings referenced as ’”address”.
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