SMJ320C25GBM Datasheet, PDF (22/38 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C25, SMJ320C25Ć50
DIGITAL SIGNAL PROCESSOR
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
serial port timing
switching characteristics over recommended operating conditions (see Note 1)
PARAMETER
td(CH-DX)
td(FL-DX)
td(CH-FS)
Delay time, DX valid after CLKX rising edge (see Note 8)
Delay time, DX valid after FSX falling edge (TXM = 0. see Note 8)
FSX valid after CLKX rising edge (TXM = 1 )
SMJ320C25-50
MIN MAX
75
40
40
SMJ320C25
MIN MAX
80
45
45
UNIT
ns
ns
ns
timing requirements over recommended operating conditions (see Note 1)
SMJ320C25-50
MIN
MAX
SMJ320C25
MIN MAX
UNIT
fsx
Serial port frequency
1.25
6250 1.25
5000 kHz
tc(SCK)
Serial port clock (CLKX/CLKR) cycle time
160 800 000 200 800 000 ns
tw(SCK1
Serial port clock (CLKX/CLKR) low pulse duration (see Note 9)
64
80
ns
tw(SCK)
Serial port clock (CLKX/CLKR) high pulse duration (see Note 9)
64
80
ns
tsu(FS)
FSX/FSR setup time before CLKX/CLKR falling edge (TXM = 0)
5
18
ns
th(FS)
FSX/FSR hold time after CLKX/CLKR falling edge (TXM = 0)
10
20
ns
tsu(DR)
OR setup time before CLKR falling edge
5
10
ns
th(DR)
OR hold time after CLKR falling edge
10
20
ns
NOTES: 1: Q = 1/4tc(C)
8. The last occurrence of FSX falling and CLKX rising.
9. The duty cycle of the serial port clock must be within 40–60% .Serial port clock (CLKX/CLKR) rise and fall times must be less than
25 ns.
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