SMJ320C25GBM Datasheet, PDF (20/38 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

SMJ320C25, SMJ320C25Ć50
DIGITAL SIGNAL PROCESSOR
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
2.0 V
1.88 V
0.92 V
0.80 V
0
(a) Input
VIH (Min)
VIL (Max)
2.4 V
2.2 V
0.8 V
0.6 V
0
Figure 4. Voltage Reference Levels
(b) Output
VOH (Min)
VOL (Max)
switching characteristics over recommended operating conditions (see Note 1)
PARAMETER
td(C1_–S) STRB from CLKOUT1 (if STRB is present)
td(C2_–S) CLKOUT2 to STRB (if STRB is present)
tsu(A) Address setup time before STRB low (see Note 3)
th(A) Address hold time after STRB high (see Note 3)
tw(SL) STRB low pulse duration (no wait states, see Note 4)
tw(SH) STRB high pulse duration (between consecutive cycles, see Note 4)
tsu(D)W Data write setup time before STRB high (no wait states)
th(D)W Data write hold time from STRB high
ten(D) Data bus starts being driven after STRB low (write cycle)
tdis(D) Data bus three-state after STRB high (write cycle)
td(MSC) MSC valid from CLKOUT1
† _{These values are derived from characterization data and not tested.}
SMJ320C25-50
SMJ320C25
MIN MAX
MIN TYP MAX
Q–5 Q+3 Q–6
Q Q+6
–2
5
–6
0
6
Q – 13
Q – 12
Q–4
Q–8
2Q – 5 2Q + 5 2Q – 5 2Q 2Q + 5
2Q – 5 2Q + 5 2Q – 5
2Q + 5
2Q – 17
2Q – 20
Q–5
0^†
Q + 15^†
Q – 10
0^†
Q
Q Q + 15^†
–5
10
–10
0
10
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
timing requirements over recommended operating conditions (see Note 1)
SMJ320C25-50
MIN MAX
SMJ320C25
UNIT
MIN MAX
ta(A)
Access time, read data from address time (read cycle, see Notes 3 and 5)
3Q – 31
3Q – 35 ns
tsu(D)R
Setup time, data read before STRB high
17
23
ns
th(D)R
Hold time, data read from STRB high
0
0
ns
td(SL_–R)
Delay time, READY valid after STRB low (no wait states)
Q – 20
Q – 20 ns
td(C2H_–R)
Delay time, READY valid after CLKOUT2 high
Q – 21
Q – 20 ns
th(SL_–R)
Hold time, READY after STRB low (no wait states)
Q–1
Q+3
ns
th(C2H_–R)
Hold time, READY after CLKOUT2 high
Q–1
Q+3
ns
td(M_–R)
Delay time, READY valid after MSC valid
2Q – 25
2Q – 25 ns
th(M_–R)
Hold time, READY after MSC valid
0
0
ns
NOTES: 1: 0 = 1/4tc(C)
3. A15–A0, PS, DS, IS, R/W, and BR timings are all included in timings referenced as ”address”
4. Delays between CLKOUT1 /CLKOUT2 edges and STRB edges track each other, resulting in tw(SL) and tw(SH) being 2Q with no
wait states.
5. Read data access time is defined as ta(A) = tsu(A) + tw(SL) – tsu(D)R + tr(C).
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