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OMAP3515DCUS Datasheet, PDF (5/264 Pages) Texas Instruments – OMAP3515 and OMAP3503 Applications Processors
OMAP3515, OMAP3503
www.ti.com
SPRS505H – FEBRUARY 2008 – REVISED OCTOBER 2013
Table 1-1. Differences Between CBB, CBC, and CUS Packages
FEATURE
Pin Assignments
Package-On-Package (POP)
Interface
Discrete Memory Interface
GPMC
UART1
UART2
McBSP3
GP Timer
McBSP4
HSUSB3_TLL
MM_FSUSB3
McSPI1
MMC3
CBB PACKAGE
For CBB package pin
assignments see Table 2-1, Ball
Characteristics (CBB Pkg.)
CBC PACKAGE
For CBC package pin
assignments see Table 2-2, Ball
Characteristics (CBC Pkg.)
CUS PACKAGE
For CUS package pin
assignments see Table 2-3, Ball
Characteristics (CUS Pkg.)
POP interface supported
POP interface supported
POP interface not available
Discrete Memory Interface
supported
Eight chip-select pins available
Discrete Memory Interface not
supported
Eight chip-select pins available
Four wait pins available
Four wait pins available
CTS signal is available on 3 pins
(triple muxed): uart1_cts (AG22 /
W8 / T21), uart1_rts (AH22 /
AA9), uart1_tx (F28 / Y8 / AE7),
uart1_rx (E26 / AA8)
The following signals are either
available on two (double muxed)
or three pins (triple muxed):
uart1_cts (AE21 / T19 / W2),
uart1_rts (AE22 / R2), uart1_rx
(H3 / H25 / AE4), uart1_tx (L4 /
G26)
The following signals are
available on two pins (double
muxed): uart2_cts (AF6/AB26),
uart2_rts (AE6/AB25), uart2_tx
(AF5/AA25), uart2_rx
(AE5/AD25)
The following signals are
available on two pins (double
muxed): uart2_cts (Y24/P3),
uart2_rts (AA24/N3), uart2_tx
(AD22/U3), uart2_rx (AD21/W3)
The following signals are
The following signals are
available on three pins (triple
available on two pins (triple
muxed): mcbsp3_dx (AF6 / AB26 muxed): mcbsp3_dx (U17/ Y24/
/ V21), mcbsp3_dr (AE6 / AB25 / P3), mcbsp3_dr (T20/ AA24 /
U21), mcbsp3_clkx (AF5 / AA25 / N3), mcbsp3_clkx (T17/ AD22 /
W21), and mcbsp3_fsx (AE5 / U3), mcbsp3_fsx (P20/ AD21 /
AD25 / K26)
W3)
The following signals are
available on three pins (triple
muxed): gpt8_pwm_evt (N8 /
AD25 / V3), gpt9_pwm_evt (T8 /
AB26 / Y2), gpt10_pwm_evt (R8
/ AB25 / Y3), and
gpt11_pwm_evt (P8 / AA25 / Y4)
The following signals are
available on three pins (triple
muxed): gpt8_pwm_evt
(C5/AD21/V9), gpt9_pwm_evt
(B4/W8/Y24),
gpt10_pwm_evt(C4/U8/AA24),
gpt11_pwm_evt(B5/V8/AD22)
The following signals are
available on two pins (double
muxed): mcbsp4_clkx (T8/AE1),
mcbsp4_dr (R8/AD1),
mcbsp4_dx (P8/AD2),
mcbsp4_fsx (N8/AC1)
The following signals are
available on two pins (double
muxed): mcbsp4_clkx (B4 / V3),
mcbsp4_dr (C4 / U4),
mcbsp4_dx (B5 / R3),
mcbsp4_fsx (C5 / T3)
Supported
Supported
Supported
Supported
Four chip-select pins are
available
Four chip-select pins are
available
The following signals are
available on two pins (double
muxed): mmc3_cmd (AC3 /
AE10), and mmc3_clk (AB1 /
AF10)
The following signals are
available on two pins (double
muxed): mmc3_cmd (R8 / AB3),
mmc3_clk (R9 / AB2)
Discrete Memory Interface
supported
Chip-select pins gpmc_ncs1 and
gpmc_ncs2 are not available
Wait pins gpmc_wait1 and
gpmc_wait2 are not available
CTS signal is available on 3 pins
(triple muxed): uart1_cts (AC19 /
AC2 / AA18), uart1_rts (W6 /
AB19), uart1_tx (E23 / V7 / AC3),
uart1_rx (D24 / W7)
The following signals are
available on one pin only:
uart2_cts (V6), uart2_rts (V5),
uart2_tx (W4), uart2_rx (V4)
The following signals are
available on two pins only
(double muxed): mcbsp3_dx
(V6/W18), mcbsp3_dr (V5/Y18),
mcbsp3_clkx (W4/V18), and
mcbsp3_fsx (V4/AA19)
The following signals are
available on two pins only
(double muxed): gpt8_pwm_evt
(G4/M4), gpt9_pwm_evt (F4/N4),
gpt10_pwm_evt (G5/N3), and
gpt11_pwm_evt (F3/M5)
The following signals are
available on one pin only:
mcbsp4_clkx (F4), mcbsp4_dr
(G5), mcbsp4_dx (F3),
mcbsp4_fsx (G4)
Not supported
Not supported
Chip-select pins mcspi1_cs1 and
mcspi_cs2 are not available
The following signals are
available on one pin only:
mmc3_cmd (AD3), and
mmc3_clk (AC1)
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OMAP3515 and OMAP3503 Applications Processors
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