OMAP3515DCUS Datasheet, PDF (224/264 Pages) Texas Instruments – OMAP3515 and OMAP3503 Applications Processors

OMAP3515, OMAP3503
SPRS505H – FEBRUARY 2008 – REVISED OCTOBER 2013
www.ti.com
Table 6-100. High-Speed USB Switching Characteristics – 12-bit Master Mode⁽¹⁾ (continued)
N O.
t_d(clkL-DIV)
t_R(do)
t_F(do)
PARAMETER
Delay time, hsusbx_clk high to output hsusbx_data[0:7] invalid
Rise time, output signals
Fall time, output signals
1.15 V
MIN
MAX
2
2
2
UNIT
ns
ns
ns
HSU0
hsusbx_clk
hsusbx_stp
HSU1
HSU1
HSU3
hsusbx_dir_&_nxt
hsusbx_data[7:0]
HSU2
HSU2
Data_OUT
HSU5
Data_IN
In hsusbx, x is equal to 1 or 2.
Figure 6-50. High-Speed USB – 12-bit Master Mode
HSU4
HSU6
030-087
6.6.4.3 High-Speed Universal Serial Bus (USB) on Ports 1, 2, and 3 – 12-bit TLL Master Mode
Table 6-102 and Table 6-103 assume testing over the recommended operating conditions (see Figure 6-
51).
Table 6-101. High-Speed USB Timing Conditions – 12-bit TLL Master Mode
TIMING CONDITION PARAMETER
Input Conditions
t_R
t_F
Output Conditions
Input signal rise time
Input signal fall time
C_LOAD
Output load capacitance
VALUE
2
2
3
UNIT
ns
ns
pF
Table 6-102. High-Speed USB Timing Requirements – 12-bit TLL Master Mode⁽¹⁾
NO.
PARAMETER
HSU2 t_s(STPV-CLKH)
Setup time, hsusbx_tll_stp valid before hsusbx_tll_clk rising edge
HSU3 t_{s(CLKH-STPIV)}
Hold time, hsusbx_tll_stp valid after hsusbx_tll_clk rising edge
HSU4 t_{s(DATAV-CLKH)}
Setup time, hsusbx_tll_data[7:0] valid before hsusbx_tll_clk rising edge
HSU5 t_{h(CLKH-DATIV)}
Hold time, hsusbx_tll_data[7:0] valid after hsusbx_tll_clk rising edge
(1) In hsusbx, x is equal to 1, 2, or 3.
1.15 V
MIN
MAX
6
0
6
0
UNIT
ns
ns
ns
ns
Table 6-103. High-Speed USB Switching Characteristics – 12-bit TLL Master Mode⁽¹⁾
NO.
HSU0 f_p(CLK)
PARAMETER
hsusbx_tll_clk clock frequency
1.15 V
MIN
MAX
60
UNIT
MHz
(1) In hsusbx, x is equal to 1, 2, or 3.
224 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS
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