OMAP3515DCUS Datasheet, PDF (138/264 Pages) Texas Instruments – OMAP3515 and OMAP3503 Applications Processors

OMAP3515, OMAP3503
SPRS505H – FEBRUARY 2008 – REVISED OCTOBER 2013
www.ti.com
Table 4-9 details the input requirements of the input clock.
Table 4-9. 48- or 54-MHz Input Clock Source Timing Requirements^{(1) (2)}
NAME
DESCRIPTION
MIN
TYP
MAX
UNIT
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
1 / t_c(altclk)
t_w(altclk)
t_J(altclk)
t_R(altclk)
t_F(altclk)
t_J(altclk)
Frequency, sys_altclk
Pulse duration, sys_altclk low or
high
Peak-to-peak jitter⁽¹⁾, sys_altclk
Rise time, sys_altclk
Fall time, sys_altclk
Frequency stability, sys_altclk
48-, 54-, or up to 59- MHz
0.40 * t_c(altclk)
0.60 * t_c(altclk)
–1%
1%
10
10
± 50
MHz
ns
ns
ns
ppm
(1) Peak-to-peak jitter is defined as the difference between the maximum and the minimum output periods on a statistical population of 300
period samples. The sinusoidal noise is added on top of the vdds supply voltage.
(2) See Table 3-4, Electrical Characteristics, for sys_altclk V_IH/V_IL parameters.
sys_altclk
ALT0
Figure 4-6. Alternate CMOS Clock
ALT1
ALT1
030-013
138 CLOCK SPECIFICATIONS
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