OMAP3515DCUS Datasheet, PDF (29/264 Pages) Texas Instruments – OMAP3515 and OMAP3503 Applications Processors

OMAP3515, OMAP3503
www.ti.com
SPRS505H – FEBRUARY 2008 – REVISED OCTOBER 2013
Table 2-1. Ball Characteristics (CBB Pkg.)⁽¹⁾ (continued)
BALL
BALL TOP PIN NAME MODE [4] TYPE [5]
BOTTOM [1] [2]
[3]
safe_mode 7
K1
M2
gpmc_d0 0
IO
L1
M1
gpmc_d1 0
IO
L2
N2
gpmc_d2 0
IO
P2
N1
gpmc_d3 0
IO
T1
R2
gpmc_d4 0
IO
V1
R1
gpmc_d5 0
IO
V2
T2
gpmc_d6 0
IO
W2
T1
gpmc_d7 0
IO
H2
AB3
gpmc_d8 0
IO
gpio_44
4
IO
safe_mode 7
K2
AC3
gpmc_d9 0
IO
gpio_45
4
IO
safe_mode 7
P1
AB4
gpmc_d10 0
IO
gpio_46
4
IO
safe_mode 7
R1
AC4
gpmc_d11 0
IO
gpio_47
4
IO
safe_mode 7
R2
AB6
gpmc_d12 0
IO
gpio_48
4
IO
safe_mode 7
T2
AC6
gpmc_d13 0
IO
gpio_49
4
IO
safe_mode 7
W1
AB7
gpmc_d14 0
IO
gpio_50
4
IO
safe_mode 7
Y1
AC7
gpmc_d15 0
IO
gpio_51
4
IO
safe_mode 7
G4
Y2
gpmc_ncs0 0
O
H3
Y1
gpmc_ncs1 0
O
gpio_52
4
IO
safe_mode 7
V8
NA
gpmc_ncs2 0
O
gpio_53
4
IO
safe_mode 7
U8
NA
gpmc_ncs3 0
O
sys_
1
I
ndmareq0
gpio_54
4
IO
safe_mode 7
T8
NA
gpmc_ncs4 0
O
sys_
1
I
ndmareq1
mcbsp4_ 2
IO
clkx
gpt9_pwm_e 3
IO
vt
gpio_55
4
IO
safe_mode 7
R8
NA
gpmc_ncs5 0
O
sys_
1
I
ndmareq2
BALL
RESET
STATE [6]
BALL
RESET REL. POWER [9] HYS [10]
RESET REL. MODE [8]
STATE [7]
H
H
0
vdds_ mem Yes
H
H
0
vdds_ mem Yes
H
H
0
vdds_ mem Yes
H
H
0
vdds_ mem Yes
H
H
0
vdds_ mem Yes
H
H
0
vdds_ mem Yes
H
H
0
vdds_ mem Yes
H
H
0
vdds_ mem Yes
H
H
0
vdds_ mem Yes
H
H
0
vdds_ mem Yes
H
H
0
vdds_ mem Yes
H
H
0
vdds_ mem Yes
H
H
0
vdds_ mem Yes
H
H
0
vdds_ mem Yes
H
H
0
vdds_ mem Yes
H
H
0
vdds_ mem Yes
1
1
0
vdds_ mem No
H
1
0
vdds_ mem Yes
H
H
7
vdds_ mem Yes
H
H
7
vdds_ mem Yes
H
H
7
vdds_ mem Yes
H
H
7
vdds_ mem Yes
BUFFER PULLUP
STRENG TH /DOWN
(mA) [11] TYPE [12]
IO CELL [13]
4
PU/ PD
LVCMOS
4
PU/ PD
LVCMOS
4
PU/ PD
LVCMOS
4
PU/ PD
LVCMOS
4
PU/ PD
LVCMOS
4
PU/ PD
LVCMOS
4
PU/ PD
LVCMOS
4
PU/ PD
LVCMOS
4
PU/ PD
LVCMOS
4
PU/ PD
LVCMOS
4
PU/ PD
LVCMOS
4
PU/ PD
LVCMOS
4
PU/ PD
LVCMOS
4
PU/ PD
LVCMOS
4
PU/ PD
LVCMOS
4
PU/ PD
LVCMOS
4
NA
LVCMOS
4
PU/ PD
LVCMOS
4
PU/ PD
LVCMOS
4
PU/ PD
LVCMOS
4
PU/ PD
LVCMOS
4
PU/ PD
LVCMOS
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