DS92LX1621_16 Datasheet, PDF (5/49 Pages) Texas Instruments – 10 - 50 MHz DC-Balanced Channel Link III Serializer and Deserializer with Bi-Directional Control Channel

www.ti.com
DS92LX1622 PIN DIAGRAM
Top View
DS92LX1621, DS92LX1622
SNLS327I – MAY 2010 – REVISED JANUARY 2014
PASS
RES
RES
V_DDCML
RIN+
RIN-
BISTEN
V_DDPLL
RES
M/S
30 29 28 27 26 25 24 23 22 21
DS92LX1622
Deserializer
40-Pin WQFN
12 3
4
5
67
8
9 10
ROUT[4]
ROUT[5]
ROUT[6]
ROUT[7]
V_DDOR2
ROUT[8]
ROUT[9]
V_DDD
ROUT[10]
ROUT[11]
Figure 5. Deserializer - DS92LX1622
40-Pin WQFN (RTA Package)
DS92LX1622 Deserializer PIN DESCRIPTIONS
Pin Name
Pin No.
I/O, Type
Description
LVCMOS PARALLEL INTERFACE
ROUT[13:0]
9, 10, 11, 12,
14, 15, 17, 18,
19, 20, 21, 22,
23, 24
Outputs, LVCMOS Parallel data outputs.
HSYNC
7
Output, LVCMOS Parallel data output 14, typically used as Horizontal SYNC output
VSYNC
6
Output, LVCMOS Parallel data output 14, typically used as Vertical SYNC output
PCLK
5
Output, LVCMOS
Pixel Clock Output Pin.
Strobe edge set by RRFB control register
General Purpose Input Output (GPIO)
ROUT[3:0] /
GPIO[5:2]
21, 22, 23, 24
Input/Output, Digital
ROUT[3:0] general-purpose pins can be individually configured as either inputs
or outputs; used to control and respond to various commands.
GPIO[1:0]
26, 27
Input/Output, Digital
SERIAL CONTROL BUS - I²C COMPATIBLE
General-purpose pins can be individually configured as either inputs or outputs;
used to control and respond to various commands.
SCL
3
Input/Output, Digital
Clock line for the serial control bus communication
SCL requires an external pull-up resistor to V_DDIO.
Copyright © 2010–2014, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Links: DS92LX1621 DS92LX1622