DS92LX1621_16 Datasheet, PDF (18/49 Pages) Texas Instruments – 10 - 50 MHz DC-Balanced Channel Link III Serializer and Deserializer with Bi-Directional Control Channel

DS92LX1621, DS92LX1622
SNLS327I – MAY 2010 – REVISED JANUARY 2014
www.ti.com
Addr
(Hex)
0
Name
I²C Device ID
1
Reset
2
Reserved
CRC Fault Tolerant
Transmission
CRC Fault Tolerant
Transmission
VDDIO Control
3
VDDIO Mode
I²C Pass-Through
Reserved
PCLK_AUTO
TRFB
4
CRC Transmission
Table 1. DS92LX1621 Control Registers
Bits Field
R/W
7:1 DEVICE ID
RW
0
SER ID
RW
7:3 RESERVED
2
STANDBY
RW
1
DIGITAL RESET0
RW
0
DIGITAL RESET1
RW
7:0 RESERVED
RX CRC
7
CHECKER
RW
ENABLE
6
TX CRC GEN
ENABLE
RW
5
VDDIO CONTOL
RW
4
VDDIO MODE
RW
3
I²C PASS-
THROUGH
RW
2
RESERVED
1
PCLK_AUTO
RW
0
TRFB
RW
7:6 RESERVED
5
CRC RESET
RW
4:0 RESERVED
Default
0x58
0
0
0
0
self clear
0
self clear
0x20'h
1
1
1
1
1
0
1
1
01'b
0
0
Description
7-bit address of Serializer; 0x58h
(1011_000X) default
0: Device ID is from CAD
1: Register I²C Device ID overrides CAD
Reserved
Standby mode control. Retains control
register data. Supported only when M/S =
0
0: Enabled. Low-current Standby mode
with wake-up capability. Suspends all
clocks and functions.
1: Disabled. Standby and wake-up
disabled
1: Resets the device to default register
values. Does not affect device I²C Bus or
Device ID
1: Digital Reset, retains all register values
Reserved
Back Channel CRC Enable
0: Disable
1: Enable
For propper CRC operation, control
register 0x03h b[6] of the Deserializer
must be enabled.
Forward Channel CRC Enable
0: Disable
1: Enable
For propper CRC operation, control
register 0x03h b[7] of the Deserializer
must be enabled.
Auto V_DDIO detect
0: Disable
1: Enable (auto detect mode)
VDDIO voltage set
Only used when VDDIOCONTROL = 0
0: 1.8V
1: 3.3V
I²C Pass-Through Mode
0: Disabled
1: Enabled
Reserved
Switch over to internal 25 MHz oscillator
clock in the absence of PCLK
0: Disable
1: Enable
Pixel Clock Edge Select:
0: Parallel Interface Data is strobed on
the Falling Clock Edge.
1: Parallel Interface Data is strobed on
the Rising Clock Edge.
Reserved
1: CRC Reset.
Clears CRC Error counter.
Reserved
18
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