DS92LX1621_16 Datasheet, PDF (4/49 Pages) Texas Instruments – 10 - 50 MHz DC-Balanced Channel Link III Serializer and Deserializer with Bi-Directional Control Channel

DS92LX1621, DS92LX1622
SNLS327I – MAY 2010 – REVISED JANUARY 2014
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DS92LX1621 Serializer PIN DESCRIPTIONS (continued)
Pin Name
Pin No.
I/O, Type
SERIAL CONTROL BUS - I²C COMPATIBLE
SCL
4
Input/Output, Digital
SDA
5
Input/Output, Open
Drain
M/S
8
Input, LVCMOS w/
pull down
CAD
6
Input, analog
CONTROL AND CONFIGURATION
PDB
9
Input, LVCMOS w/
pull down
RES
7
Channel Link III INTERFACE
DOUT+
13
DOUT-
12
Power and Ground
VDDPLL
10
VDDT
11
VDDCML
14
VDDD
28
VDDIO
25
VSS
DAP
Input, LVCMOS w/
pull down
Input/Output, CML
Input/Output, CML
Power, Analog
Power, Analog
Power, Analog
Power, Digital
Power, Digital
Ground, DAP
Description
Clock line for the serial control bus communication
SCL requires an external pull-up resistor to V_DDIO.
Data line for the serial control bus communication
SDA requires an external pull-up resistor to V_DDIO.
I²C Mode Select
M/S = L, Master (default); device generates and drives the SCL clock line
M/S = H, Slave; device accepts SCL clock input
Continuous Address Decoder
Input pin to select the Slave Device Address.
Input is connect to external resistor divider to programmable Device ID
address (See Figure 29).
Power down Mode Input Pin.
PDB = H, Transmitter is enabled and is ON.
PDB = L, Transmitter is in Sleep (Power Down). When the transmitter is in the
SLEEP state, the PLL is shutdown, and IDD is minimized.
Reserved. This pin MUST be tied LOW.
Non-inverting differential output, back-channel input.
Inverting differential output, back-channel input.
PLL Power, 1.8V ±5%
Tx Analog Power, 1.8V ±5%
LVDS & BC Dr Power, 1.8V ±5%
Digital Power, 1.8V ±5%
Power for input stage, The single-ended inputs are powered from V_DDIO.
DAP must be grounded. Connect to ground plane with at least 9 vias.
4
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