DS90LV047A_16 Datasheet, PDF (5/25 Pages) Texas Instruments – 3-V LVDS Quad CMOS Differential Line Driver

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DS90LV047A
SNLS044D – MAY 2000 – REVISED JULY 2016
Electrical Characteristics (continued)
Over supply voltage and operating temperature ranges, unless otherwise specified^(1)(2)(3)
PARAMETER
TEST CONDITIONS
PIN
MIN
I_OS
Output short-circuit current⁽⁴⁾
I_OSD
Differential output short-circuit
current ⁽⁴⁾
I_OFF
Power-off leakage
ENABLED,
D_IN = V_CC, D_OUT+ = 0 V or
D_IN = GND, D_OUT− = 0 V
ENABLED, V_OD = 0 V
D_OUT−
V_OUT = 0 V or 3.6 V, V_CC = 0 V or
Open
D_OUT+
−20
I_OZ
Output TRI-STATE current
EN = 0.8 V and EN* = 2.0 V
V_OUT = 0 V or V_CC
−10
I_CC
No load supply current drivers enabled D_IN = V_CC or GND
I_CCL
Loaded supply current drivers enabled
R_L = 100 Ω all channels, D_IN = V_CC
or GND (all inputs)
V_CC
I_CCZ
No load supply current drivers
disabled
D_IN = V_CC or GND, EN = GND,
EN* = V_CC
(4) Output short circuit current (I_OS) is specified as magnitude only, minus sign indicates direction only.
TYP MAX UNIT
−4.2
−9 mA
−4.2
±1
±1
4
20
2.2
−9 mA
20 µA
10 µA
8 mA
30 mA
6 mA
6.6 Switching Characteristics
V_CC = +3.3V ± 10%, T_A = −40°C to +85°C^(1)(2)(3)
PARAMETER
TEST CONDITIONS
t_PHLD
Differential propagation delay high to
low
t_PLHD
t_SKD1
t_SKD2
t_SKD3
t_SKD4
t_TLH
t_THL
t_PHZ
t_PLZ
t_PZH
t_PZL
f_MAX
Differential propagation delay low to
high
Differential pulse skew |t_PHLD − t_PLHD|⁽⁴⁾
Channel-to-channel skew⁽⁵⁾
Differential part-to-part skew⁽⁶⁾
Differential part-to-part skew⁽⁷⁾
Rise time
Fall time
Disable time high to Z
Disable time low to Z
Enable time Z to high
Enable time Z to low
Maximum operating frequency⁽⁸⁾
R_L = 100 Ω, C_L = 15 pF
(Figure 18 and Figure 19)
R_L = 100 Ω, C_L = 15 pF
(Figure 20 and Figure 21)
MIN TYP MAX UNIT
0.5
0.9
1.7 ns
0.5
1.2
0
0.3
0
0.4
0
0
0.5
0.5
2
2
3
3
200
250
1.7 ns
0.4 ns
0.5 ns
1 ns
1.2 ns
1.5 ns
1.5 ns
5 ns
5 ns
7 ns
7 ns
MHz
(1) All typicals are given for: V_CC = 3.3 V, T_A = +25°C.
(2) Generator waveform for all tests unless otherwise specified: f = 1 MHz, Z_O = 50 Ω, t_r ≤ 1 ns, and t_f ≤ 1 ns.
(3) C_L includes probe and jig capacitance.
(4) t_SKD1 |t_PHLD – t_PLHD| is the magnitude difference in differential propagation delay time between the positive going edge and the negative
going edge of the same channel.
(5) t_SKD2 is the differential channel-to-channel skew of any event on the same device.
(6) t_SKD3, differential part-to-part skew, is defined as the difference between the minimum and maximum specified differential propagation
delays. This specification applies to devices at the same V_CC and within 5°C of each other within the operating temperature range.
(7) t_SKD4, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices
over recommended operating temperature and voltage ranges, and across process distribution. t_SKD4 is defined as |Max − Min|
differential propagation delay.
(8) f_MAX generator input conditions: t_r = t_f < 1 ns (0% to 100%), 50% duty cycle, 0 V to 3 V. Output criteria: duty cycle = 45% / 55%,
VOD > 250 mV, all channels switching.
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