BQ25700A Datasheet, PDF (5/82 Pages) Texas Instruments – SMBus Multi-Chemistry Battery Buck-Boost Charge Controller With System Power Monitor and Processor Hot Monitor

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PIN
NAME
NUMBER
CHRG_OK
4
CMPIN
14
CMPOUT
15
COMP2
17
COMP1
16
EN_OTG
5
HIDRV1
31
HIDRV2
24
IADPT
8
IBAT
9
ILIM_HIZ
6
LODRV1
29
LODRV2
26
PGND
27
PROCHOT
11
PSYS
10
REGN
28
SCL
13
SDA
12
Pin Functions (continued)
bq25700A
SLUSCQ8 – MAY 2017
I/O
O
I
I
I
I
I
O
O
O
O
I
O
O
GND
O
O
PWR
I
I/O
DESCRIPTION
Open drain active high indicator to inform the system good power source is connected to the
charger input. Connect to the pullup rail via 10-kΩ resistor. When VBUS rises above 3.5V or
falls below 24.5V, CHRG_OK is HIGH after 50ms deglitch time. When VBUS is falls below
3.2 V or rises above 26 V, CHRG_OK is LOW.
Input of independent comparator. The independent comparator compares the voltage sensed
on CMPIN pin to internal reference, and its output is on CMPOUT pin. Internal reference,
output polarity and deglitch time is selectable by SMBus. With polarity HIGH (REG0x30[6] =
1), place a resistor between CMPIN and CMPOUT to program hysteresis. With polarity LOW
(REG0x30[6] = 0), the internal hysteresis is 100 mV. If the independent comparator is not in
use, tie CMPIN to ground.
Open-drain output of independent comparator. Place pullup resistor from CMPOUT to pullup
supply rail. Internal reference, output polarity and deglitch time are selectable by SMBus.
Buck boost converter compensation pin 2. Refer to bq25700 EVM schematic for COMP2 pin
RC network.
Buck boost converter compensation pin 1. Refer to bq25700 EVM schematic for COMP1 pin
RC network.
Active HIGH to enable OTG mode. When EN_OTG pin is HIGH and REG0x32[13] is HIGH,
OTG can be enabled, refer to USB On-The-Go (OTG) for details of how to enable OTG
function
Buck mode high side power MOSFET (Q1) driver. Connect to high side n-channel MOSFET
gate.
Boost mode high side power MOSFET(Q4) driver. Connect to high side n-channel MOSFET
gate.
Buffered adapter current output. V_(IADP) = 20 or 40 × (V_(ACP) – V_(ACN)). With ratio selectable in
REG0x12[4]. Place a resistor from the IADPT pin to ground corresponding to inductor in use.
For 2.2 µH, the resistor is 137 kΩ. Place 100-pF or less ceramic decoupling capacitor from
IADPT pin to ground. IADPT output voltage is clamped below 3.3 V.
Buffered battery current selected by SMBus. V_(IBAT) = 8 or 16 × (V_(SRP) – V_(SRN)) for charge
current, or V_(IBAT) = 8 or 16 × (V_(SRN) – V_(SRP)) for discharge current, with ratio selectable in
REG0x12[3]. Place 100-pF or less ceramic decoupling capacitor from IBAT pin to ground.
This pin can be floating if not in use. Its output voltage is clamped below 3.3 V.
Input current limit input. Program ILIM_HIZ voltage by connecting a resistor divider from
supply rail to ILIM_HIZ pin to ground. The pin voltage is calculated as: V_{(ILIM_HIZ)} = 1 V + 40
× IDPM × RAC, in which IDPM is the target input current. The input current limit used by the
charger is the lower setting of ILIM_HIZ pin and REG0x3F(). When the pin voltage is below
0.4 V, the device enters Hi-Z mode with low quiescent current. When the pin voltage is
above 0.8 V, the device is out of Hi-Z mode.
Buck mode low side power MOSFET (Q2) driver. Connect to low side n-channel MOSFET
gate.
Boost mode low side power MOSFET (Q3) driver. Connect to low side n-channel MOSFET
gate.
Device power ground.
Active low open drain output of processor hot indicator. It monitors adapter input current,
battery discharge current, and system voltage. After any event in the PROCHOT profile is
triggered, a minimum 10-ms pulse is asserted. The pulse width is adjustable in
REG0x33[5:2].
Current mode system power monitor. The output current is proportional to the total power
from the adapter and battery. The gain is selectable through SMBus. Place resistor from
PSYS to ground to generate output voltage. This pin can be floating if not in use. Its output
voltage is clamped below 3.3 V. Place a capacitor in parallel with resistor for filtering.
6-V linear regulator output supplied from VBUS or VSYS. The LDO is active when VBUS
above V_{VBUS_CONVEN}. Connect a 2.2- or 3.3-μF ceramic capacitor from REGN to power
ground. REGN pin output is for power stage gate drive.
SMBus clock input. Connect to clock line from the host controller or smart battery. Connect a
10-kΩ pullup resistor according to SMBus specifications.
SMBus open-drain data I/O. Connect to data line from the host controller or smart battery.
Connect a 10-kΩ pullup resistor according to SMBus specifications.
Copyright © 2017, Texas Instruments Incorporated
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