BQ25700A Datasheet, PDF (30/82 Pages) Texas Instruments – SMBus Multi-Chemistry Battery Buck-Boost Charge Controller With System Power Monitor and Processor Hot Monitor

bq25700A
SLUSCQ8 – MAY 2017
www.ti.com
Programming (continued)
8.5.1.1 SMBus Write-Word and Read-Word Protocols
Table 4. Write-Word Format
S
(1) (2)
SLAVE
ADDRESS ⁽¹⁾
7 bits
MSB LSB
W
(1) (3)
1b
0
ACK
(4) (5)
1b
0
COMMAND
BYTE ⁽¹⁾
8 bits
MSB LSB
ACK
(4) (5)
1b
0
LOW DATA
BYTE ⁽¹⁾
8 bits
MSB LSB
ACK
(4) (5)
1b
0
(1) Master to slave
(2) S = Start condition or repeated start condition
(3) W = Write bit (logic-low)
(4) Slave to master (shaded gray)
(5) ACK = Acknowledge (logic-low)
(6) P = Stop condition
HIGH DATA
BYTE ⁽¹⁾
8 bits
MSB LSB
ACK
(4) (5)
1b
0
P
(1) (6)
Table 5. Read-Word Format
S⁽¹⁾ SLAVE
W ACK COMMAND ACK S⁽¹⁾ SLAVE R⁽¹⁾ ACK LOW DATA ACK HIGH DATA NACK P
(2) _ADDRESS (1) (1) (3) (4) (5) _BYTE (1) (4) (5) (2) _ADDRESS (1) (6) (4) (5) _BYTE (4) (1) (5)
BYTE ⁽⁴⁾
(1) (7) (1) (8)
7 bits
1b 1b
8 bits
1b
7 bits
1b 1b
8 bits
1b
8 bits
1b
MSB LSB
0
0 MSB LSB 0
MSB LSB 1 0 MSB LSB 0 MSB LSB
1
(1) Master to slave
(2) S = Start condition or repeated start condition
(3) W = Write bit (logic-low)
(4) Slave to master (shaded gray)
(5) ACK = Acknowledge (logic-low)
(6) R = Read bit (logic-high)
(7) NACK = Not acknowledge (logic-high)
(8) P = Stop condition
8.5.1.2 Timing Diagrams
A
B
C
D
EF
G
t_LOW t_HIGH
H
IJ
K
LM
SMBCLK
SMBDATA
t_SU:STA t_HD:STA
t_SU:DAT t_HD:DAT
t_HD:DAT
A = Start condition
B = MSB of address clocked into slave
C = LSB of address clocked into slave
D = R/W bit clocked into slave
E = Slave pulls SMBDATA line low
F = ACKNOWLEDGE bit clocked into master
G = MSB of data clocked into slave
H = LSB of data clocked into slave
I = Slave pulls SMBDATA line low
J = Acknowledge clocked into master
K = Acknowledge clock pulse
L = Stop condition, data executed by slave
M = New start condition
Figure 15. SMBus Write Timing
t_SU:STO t_BUF
30
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