BQ25700A Datasheet, PDF (33/82 Pages) Texas Instruments – SMBus Multi-Chemistry Battery Buck-Boost Charge Controller With System Power Monitor and Processor Hot Monitor

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8.6.1 Setting Charge and PROCHOT Options
8.6.1.1 ChargeOption0 Register (SMBus address = 12h) [reset = E20Eh]
bq25700A
SLUSCQ8 – MAY 2017
Figure 17. ChargeOption0 Register (SMBus address = 12h) [reset = E20Eh]
15
EN_LWPWR
R/W
14
13
WDTMR_ADJ
R/W
12
IDPM_AUTO_
DISABLE
R/W
11
OTG_ON_
CHRGOK
R/W
10
EN_OOA
R/W
9
PWM_FREQ
R/W
8
Reserved
R/W
7
6
5
4
Reserved
EN_LEARN IADPT_GAIN
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
3
IBAT_GAIN
R/W
2
EN_LDO
R/W
1
EN_IDPM
R/W
0
CHRG_INHIBIT
R/W
Table 7. ChargeOption0 Register (SMBus address = 12h) Field Descriptions
SMBus
BIT
FIELD
15 EN_LWPWR
14-13 WDTMR_ADJ
12 IDPM_AUTO_
DISABLE
11 OTG_ON_
CHRGOK
10 EN_OOA
TYPE
R/W
R/W
R/W
R/W
R/W
RESET
1b
11b
0b
0b
0b
DESCRIPTION
Low Power Mode Enable
0b: Disable Low Power Mode. Device in performance mode with battery only.
The PROCHOT, current/power monitor buffer and comparator follow register
setting.
1b: Enable Low Power Mode. Device in low power mode with battery only for
lowest quiescent current. PROCHOT, discharge current monitor buffer, power
monitor buffer and independent comparator are disabled. ADC is not available
in Low Power Mode. Independent comparator can be enabled by setting either
REG0X30()[14] or [13] to 1. <default at POR>
WATCHDOG Timer Adjust
Set maximum delay between consecutive SMBus write of charge voltage or
charge current command.
If device does not receive a write on the REG0x15() or the REG0x14() within
the watchdog time period, the charger will be suspended by setting the
REG0x14() to 0 mA.
After expiration, the timer will resume upon the write of REG0x14(),
REG0x15() or REG0x12[14:13]. The charger will resume if the values are
valid.
00b: Disable Watchdog Timer
01b: Enabled, 5 sec
10b: Enabled, 88 sec
11b: Enable Watchdog Timer, 175 sec <default at POR>
IDPM Auto Disable
When CELL_BATPRESZ pin is LOW, the charger automatically disables the
IDPM function by setting EN_IDPM (REG0x12[1]) to 0. The host can enable
IDPM function later by writing EN_IDPM bit (REG0x12[1]) to 1.
0b: Disable this function. IDPM is not disabled when CELL_BATPRESZ goes
LOW. <default at POR>
1b: Enable this function. IDPM is disabled when CELL_BATPRESZ goes
LOW.
Add OTG to CHRG_OK
Drive CHRG_OK to HIGH when the device is in OTG mode.
0b: Disable <default at POR>
1b: Enable
Out-of-Audio Enable
0b: No limit of PFM burst frequency <default at POR>
1b: Set minimum PFM burst frequency to above 25 kHz to avoid audio noise
Copyright © 2017, Texas Instruments Incorporated
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