BQ24765_15 Datasheet, PDF (5/43 Pages) Texas Instruments – SMBus-Controlled Multi-Chemistry Battery Charger With Integrated Power MOSFETs

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bq24765
SLUS999A – NOVEMBER 2009 – REVISED NOVEMBER 2015
PIN
NAME
NO.
SCL
16
SDA
15
VDDP
24
VDDSMB 17
VFB
20
VICM
14
VREF
7
Power
Pad
Pin Functions (continued)
TYPE
DESCRIPTION
I
I
P
I
I
O
P
GND
SMBus Clock input. Connect to SMBus clock line from the host controller. A 10-kohm pull-up resistor to the
host controller power rail is needed.
SMBus Data input. Connect to SMBus data line from the host controller. A 10-kohm pull-up resistor to the
host controller power rail is needed.
PWM low side driver positive 6V supply output. Connect a 1uF ceramic capacitor from VDDP to PGND pin,
close to the IC. Use for high-side driver bootstrap voltage by connecting a small signal Schottky diode from
VDDP to BOOT.
Input voltage for SMBus logic. Connect a 3.3V always supply rail, or 5V always rail to VDDSMB pin. Connect
a 0.1uF ceramic capacitor from VDDSMB to AGND for decoupling.
Battery voltage remote sense. Directly connect a Kelvin sense trace from the battery pack positive terminal to
the VFB pin to accurately sense the battery pack voltage. Place a 0.1-uF capacitor from VFB to AGND close
to the IC to filter high frequency noise.
Adapter current sense amplifier output. VICM voltage is 20 times the differential voltage across CSSP-CSSN.
Place a 100pF (max) or less ceramic decoupling capacitor from VICM to AGND.
3.3V regulated voltage output. Place a 1uF ceramic capacitor from VREF to AGND pin close to the IC. This
voltage could be used for programming the ICREF threshold. VREF can directly connect to VDDSMB as
SMBus supply, or serve as pull up supply rail for CE, ACOK and ICOUT.
Exposed pad beneath the IC. AGND and PGND star-connected only at the Power Pad plane. Always solder
Power Pad to the board, and have vias on the Power Pad plane connecting to AGND and PGND planes. It
also serves as a thermal pad to dissipate heat.
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾
MIN
MAX
UNIT
DCINP, DCINA, CSOP, CSON, CSSP, CSSN, VFB, ACOK
–0.3
30
PHASE
–1
30
EAI, EAO, FBO, VDDP, ACIN, VICM, ICOUT, ICREF, CE
Voltage
VDDSMB, SDA, SCL
–0.3
7
V
–0.3
6
VREF
–0.3
3.6
BOOT (with respect to AGND and PGND)
–0.3
36
Maximum difference voltage: CSOP–CSON, CSSP–CSSN
–0.5
0.5
V
Operating junction temperature, T_J
Storage temperature, T_stg
-40
155
°C
–55
155
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to AGND and PGND if not specified. Currents are positive into, and negative out of the specified terminal.
Consult Packaging Section of the data book for thermal limitations and considerations of packages.
7.2 ESD Ratings
V_(ESD) Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾
Charged-device model (CDM), per JEDEC specification JESD22-
C101 ⁽²⁾
VALUE
±2000
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
UNIT
V
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