BQ24765_15 Datasheet, PDF (17/43 Pages) Texas Instruments – SMBus-Controlled Multi-Chemistry Battery Charger With Integrated Power MOSFETs

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bq24765
SLUS999A – NOVEMBER 2009 – REVISED NOVEMBER 2015
Table 1. Output LC Filter Component Selection Table
bq24765 (Fs = 700 kHz)
Vin
Vout
Iout
Lout
Cout
1.5 A
4.7 µH
10 µF
19.5 V
3s/4s
12.6 V/16.8 V
3A
4.5 A
4.7 µH
3.3 µH
10 µF, 20 µF
20 µF
6A
3.3 µH
20 µF, 30 µF
1.5 A
5.6 µH
10 µF
12 V
2s
8.4 V
3A
4.5 A
4.7 µH
3.3 µH
10 µF, 20 µF
20 µF
6A
2.2 µH
20 µF, 30 µF
• Shaded areas are the most likely applications.
• External compensation can be recalculated if need other values.
• Lower current applications can use the inductance used at higher currents, but would operate in DCM more
often.
8.3.5 Converter Operation
The synchronous buck PWM converter uses a fixed frequency (700 kHz) voltage mode with feed-forward control
scheme. A type III compensation network allows using ceramic capacitors at the output of the converter. The
compensation input stage is connected between the feedback output (FBO) and the error amplifier input (EAI).
The feedback compensation stage is connected between the error amplifier input (EAI) and error amplifier output
(EAO). The LC output filter selected gives a characteristic resonant frequency that is used to determine the
compensation to ensure there is sufficient phase margin for the target bandwidth.
The
resonant
frequency,
f_o,
is
given
f_o
by:
+
2p
1
Ǹ_LoCo
An internal saw-tooth ramp is compared to the internal EAO error control signal to vary the duty-cycle of the
converter. The ramp height is one-fifteenth of the input adapter voltage making it always directly proportional to
the input adapter voltage. This cancels out any loop gain variation due to a change in input voltage, and
simplifies the loop compensation. The ramp is offset by 200 mV in order to allow zero percent duty-cycle, when
the EAO signal is below the ramp. The EAO signal is also allowed to exceed the saw-tooth ramp signal in order
to get a 100% duty-cycle PWM request. Internal gate drive logic allows achieving 99.98% duty-cycle while
ensuring the N-channel upper device always has enough voltage to stay fully on. If the BOOT pin to PHASE pin
voltage falls below 4 V for more than 3 cycles, then the high-side n-channel power MOSFET is turned off and the
low-side n-channel power MOSFET is turned on to pull the PHASE node down and recharge the BOOT
capacitor. Then the high-side driver returns to 100% duty-cycle operation until the (BOOT-PHASE) voltage is
detected to fall low again due to leakage current discharging the BOOT capacitor below the 4 V, and the
recharge pulse is reissued.
The fixed frequency oscillator keeps tight control of the switching frequency under all conditions of input voltage,
battery voltage, charge current, and temperature, simplifying output filter design and keeping it out of the audible
noise region. The type III compensation provides phase boost near the cross-over frequency, giving sufficient
phase margin.
8.3.6 Refresh BTST Capacitor
If the BOOT pin to PHASE pin voltage falls below 4 V for more than 3 cycles, then the high-side n-channel power
MOSFET is turned off and the low-side n-channel power MOSFET is turned on for 40ns to pull the PHASE node
down and recharge the BOOT capacitor. The 40ns low-side MOSFET on-time is required protect from ringing
noise, and to ensure the bootstrap capacitor is always recharged and able to keep the high-side power MOSFET
on during the next cycle.
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