BQ24765_15 Datasheet, PDF (19/43 Pages) Texas Instruments – SMBus-Controlled Multi-Chemistry Battery Charger With Integrated Power MOSFETs

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bq24765
SLUS999A – NOVEMBER 2009 – REVISED NOVEMBER 2015
8.3.12 Battery Trickle Charging
The bq24765 automatically reduces the charge current limit to a fixed 220 mA to trickle charge the battery, when
the voltage on the VFB pin falls below 2.5 V. The charge current returns to the value programmed on the
ChargeCurrent(0x14) register, when the VFB pin voltage rises above 2.7 V. This function provides a safe trickle
charge to close deeply discharged open packs.
8.3.13 High Accuracy VICM Using Current Sense Amplifier (CSA)
An industry standard, high accuracy current sense amplifier (CSA) is used to monitor the input current by the
host or some discrete logic through the analog voltage output of the VICM pin. The CSA amplifies the input
sensed voltage of CSSP-CSSN by 20x through the VICM pin. Once DCIN is above 4.5 V and ACIN is above 0.6
V, VICM no longer stays at ground, but becomes active. If the user wants to lower the voltage, they could use a
resistor divider from VICM to AGND, and still achieve accuracy over temperature as the resistors can be
matched their thermal coefficients.
A 100pF capacitor connected on the output is recommended for decoupling high-frequency noise.
8.3.14 VDDSMB Input Supply
The VDDSMB input provides bias power to the SMBus interface logic. Connect VDDSMB to an external 3.3-V or
5-V supply rail. SMBus communication can occur between host and charger when VDDSMB voltage above 2.5 V
and VREF voltage at 3.3 V. Bypass VDDSMB to AGND with a 0.1-µF or greater ceramic capacitor.
8.3.15 Input Undervoltage Lockout (UVLO)
The system must have a minimum 4.5 V DCINA voltage to allow proper operation. When the DCINA voltage is
below 4 V, VREF LDO stays inactive, even with ACIN above 0.6 V. VREF turns-on When DCINA>4.5 V and
ACIN>0.6 V. To enable VDDP requires DCINA>4.5 V, ACIN>2.4 V and CE=HIGH.
8.3.16 VDDP Gate Drive Regulator
An integrated low-dropout (LDO) linear regulator provides a 6 V supply derived from DCINP, for high efficiency,
and delivers over 90 mA of load current. The LDO powers the gate drivers of the n-channel switching MOSFETs.
Bypass VDDP to PGND with a 1-µF or greater ceramic capacitor. During thermal shut down, VDDP LDO is
disabled.
8.3.17 Input Current Comparator Trip Detection
In order to optimize the system performance, the host keeps an eye on the adapter current. Once the adapter
current is above a threshold set via ICREF, the ICOUT pin sends signal to the HOST. The signal alarms the host
that input power has exceeded the programmed limit, allowing the host to throttle back system power by reducing
clock frequency, lowering rail voltages, or disabling certain parts of the system. The ICOUT pin is an open-drain
output. Connect a pull-up resistor to ICOUT. The output is logic HI when the VICM output voltage (VICM = 20 x
V(CSSP-CSSN)) is lower than the ICREF input voltage. The ICREF threshold is set by an external resistor
divider using VREF. A hysteresis can be programmed by a positive feedback resistor from ICOUT pin to the
ICREF pin.
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